This repository contains a model of a PCI Express controller in a C library and also a SystemC / TLM 2.0 PCI Express controller model using the library.
An overview of the SystemC / TLM 2.0 PCIeController model can be seen in picture 1.
Picture 1 Overview of the PCIeController
PCIE Transaction TLM initiator sockets
Layer .----------------. (BAR0-BAR5)
[TLP packet side] | |--------------------->
| |--------------------->
| |---------------------> [User logic side]
TLM target socket | PCIeController |--------------------->
------------------>| |--------------------->
| |--------------------->
| |
TLM initiator socket | | TLM target socket
<------------------| | (DMA to the PCIE interface)
| |<---------------------
| |
| | MSI-X interrupts
| | (sc_signal vector)
| |<---------------------
'----------------'
The two connections depicted on the left side of the PCIeController communicate through TLM generic payloads containing TLP packets as data and is the PCI Express Transaction layer interface of the PCIeController (towards a potential Data link layer). The PCIeController receives TLP packets through the TLM target socket and transmits TLP packets through its TLM initiator socket. The data inside a transferred or received TLM generic payload contains one TLP packet and the data length of the TLM generic payload contains the size in bytes of the TLP packet.
The right side of PCIeController shows the interface towards user logic. There are 6 BAR TLM initiator sockets that forward translated PCI Express memory read and write requests (received on the left side of the picture) as standard TLM generic payload read and write requests through the corresponding TLM initiator BAR. There is also a DMA TLM target socket through which the user logic can perform read and write requests towards the PCI express side, incoming TLM requests on the DMA target socket will be translated and forwarded as PCI Express requests on the PCIe Express side (the left side of Picture 1) by the PCIeController.
User logic can generate MSI-X interrupts by toggling an sc_vector sc_signal on the PCIeController. The sc_vector index of the toggled sc_signal is the index of the MSI-X table entry that will be signaled by the PCIeController.
The PCIeController currently supports one physical function and is configured through a PhysFuncConfig which contains the function's configuration space (device ID, Vendor Id, number of BARs and BAR types, number MSI-X and more). The configuration is provided to the PCIeController at construction time.
Please make sure to have the /usr/include/linux/pci_regs.h header (providing
PCI defines) accessable on the build host. On a Ubuntu LTS system the header is
provided by the linux-libc-dev package.
To include and use the PCIeController model in your project you can follow the steps below. This assumes that you have cloned this repository in the root directory of your project.
See systemctlm-cosim-demo's [1] pcie/versal/cpm-qdma-demo.cc for an example project and SystemC application using the PCIeController model.
#
# SC_APP Makefile
#
PCIE_MODEL_OBJS = pcie-model/tlm-modules/pcie-controller.o
PCIE_MODEL_OBJS += pcie-model/tlm-modules/libpcie-callbacks.o
CPPFLAGS += -I pcie-model/libpcie/src -I pcie-model/
LDLIBS += libpcie.a
SC_APP_OBJS += $(PCIE_MODEL_OBJS)
# Grab the libpcie.a rule
-include pcie-model/libpcie/libpcie.mk
$(SC_APP): $(SC_APP_OBJS) libpcie.a
$(CXX) $(LDFLAGS) -o $@ $(SC_APP_OBJS) $(LDLIBS)
[1] systemctlm-cosim-demo, https://github.com/Xilinx/systemctlm-cosim-demo