systemc
There are 154 repositories under systemc topic.
verilator/verilator
Verilator open-source SystemVerilog simulator and lint system
sergeykhbr/riscv_vhdl
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
accellera-official/systemc
SystemC Reference Implementation
mariusmm/RISC-V-TLM
RISC-V SystemC-TLM simulator
tymonx/logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
intel/systemc-compiler
This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
davidepatti/noxim
Network on Chip Simulator
Xilinx/libsystemctlm-soc
SystemC/TLM-2.0 Co-simulation framework
Nic30/hwt
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
machineware-gmbh/vcml
A modeling library with virtual components for SystemC and TLM simulators
Xilinx/systemctlm-cosim-demo
QEMU libsystemctlm-soc co-simulation demos.
ultraembedded/riscv_soc
Basic RISC-V Test SoC
nelsoncsc/ISP_UVM
A Framework for Design and Verification of Image Processing Applications using UVM
Minres/SystemC-Components
A SystemC productivity library: https://minres.github.io/SystemC-Components/
AleksandarKostovic/SystemC-tutorial
Brief SystemC getting started tutorial
anikau31/systemc-clang
This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
varunnagpaal/Digital-Hardware-Modelling
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
agra-uni-bremen/crave
Constrained random stimuli generation for C++ and SystemC
tymonx/virtio
Virtio implementation in SystemVerilog
Liu-Cheng/cycle-accurate-SystemC-simulator-over-ramulator
An example of using Ramulator as memory model in a cycle-accurate SystemC Design
Xilinx/pcie-model
PCI Express controller model
xver/Shunt
SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
mitya1337/Simple_I2C
Simple implementation of I2C interface written on Verilog and SystemC
Minres/DBT-RISE-RISCV
An instruction set simulator based on DBT-RISE implementing the RISC-V ISA
jessebarreto/NetworkOnChip
Development of a Network on Chip Simulation using SystemC.
Nic30/hdlConvertorAst
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
amin-norollah/PAT-Noxim
cycle accurate Network-on-Chip Simulator
SingularityKChen/SystemC-Training
SystemC training aimed at TLM.
Minres/SystemC-Quickstart
A simple C++ CMake project to jump-start development of SystemC models and systems
agra-uni-bremen/symex-vp
A concolic testing engine for RISC-V embedded software with support for SystemC peripherals
TILhub/AMBA-3-AHB-Lite-Protocol
This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol
habedi/SystemCAccessNoxim
All you need to build and run SystemC and AccessNoxim on your system; SystemC and AccessNoxim are tools to emulate and test network-on-chip (NOC) algorithms
timurkelin/simsimd
Development and simulation framework for Application Specific Vector Processor
brilacasck/micro-acc-systemc
simulating connection of micro processor and accelerator on a bus context with systemc language
ic-lab-duth/DRIM4HLS
DUTH RISC V Microprocessor for High Level Synthesis