Zh0uzZ

Zh0uzZ's Stars

• riscv-collab/riscv-gnu-toolchain

  GNU toolchain for RISC-V, including GCC

  Language:C3.5k1.1k

• YosysHQ/picorv32

  PicoRV32 - A Size-Optimized RISC-V CPU

  Language:Verilog3.1k749

• olofk/fusesoc

  Package manager and build abstraction tool for FPGA/ASIC development

  Language:Python1.2k243

• ZipCPU/vgasim

  A Video display simulator

  Language:Verilog15517

• AlkaidDoge/Reg-Generator

  Python script which can generate Reg map xml, excel, verilog

  Language:Python62

• ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA

  Verilog Generator of Neural Net Digit Detector for FPGA

  Language:Verilog29188

• idea-fasoc/fasoc

  Language:Python5213

• OpenRunner/clash-freenode

  订阅地址🚀 免费共享♻️ 定期更新✨ 科学上网🌈 请勿滥用🚫一键订阅📪SSR/CLASH/V2RAY

  Language:Python4.6k394

• mcgodfrey/i2c-eeprom

  Controller for i2c EEPROM chip in Verilog for Mojo FPGA board

  Language:Verilog244

• sipeed/TangNano-9K-example

  TangNano-9K-example project

  Language:GLSL21870

• chipsalliance/VeeRwolf

  FuseSoC-based SoC for VeeR EH1 and EL2

  Language:Verilog28564

• alexforencich/verilog-pcie

  Verilog PCI express components

  Language:Verilog1.1k287

• hamsternz/FPGA_Webserver

  A work-in-progress for what is to be a software-free web server for static content.

  Language:VHDL78941

• hamsternz/DisplayPort_Verilog

  A Verilog implementation of DisplayPort protocol for FPGAs

  Language:Verilog23044

• osresearch/spispy

  An open source SPI flash emulator and monitor

  Language:Verilog33941

• abdelazeem201/ASIC-Design-Roadmap

  The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.

  Language:Verilog23330

• DamionGans/ubuntu-wsl2-systemd-script

  [Does not work anymore!] Script to enable systemd support on current Ubuntu WSL2 images

  Language:Shell1.6k383

• chipsalliance/verible

  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

  Language:C++1.3k204

• billryan/resume

  An elegant \LaTeX\ résumé template. 大陆镜像 https://gods.coding.net/p/resume/git

  Language:TeX9.2k2.6k

• a2824256/HLS-LeNet

  The CNN based on the Xilinx Vivado HLS

  Language:C++3510

• zachjs/sv2v

  SystemVerilog to Verilog conversion

  Language:Haskell54152

• esl-epfl/x-heep

  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V

  Language:C14175

• esl-epfl/HEEPsilon

  A low power platform based on X-HEEP and integrating the ESL-CGRA

  Language:C118

• bogini/Pong

  Pong game on an FPGA in Verilog.

  Language:Verilog4911

• abdelazeem201/ASIC_Material

  Language:Tcl32

• pConst/basic_verilog

  Must-have verilog systemverilog modules

  Language:Verilog1.6k373

• universal-ctags/ctags

  A maintained ctags implementation

  Language:C6.5k622

• MrJBSwe/fft_lcd

  fft - kendryte k210 / Sipeed M1 dock

  Language:C3310

• skywind3000/awesome-cheatsheets

  超级速查表 - 编程语言、框架和开发工具的速查表，单个文件包含一切你需要知道的东西 :zap:

  Language:Shell11.1k2k

• Zh0uzZ/sfp_fft

  Language:C++1