Pinned Repositories
ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core
berkeley-hardfloat
circuitdiagram
A user-friendly program for making electronic circuit diagrams.
circuitdiagram-vscode
Circuit Diagram extension for Visual Studio Code.
CNN-FPGA
Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database
cnnhwpe
components
Library of components for Circuit Diagram.
core_ddr3_controller
A DDR3 memory controller in Verilog for various FPGAs
coremark
CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcrontrollers (MCU).
Cores-SweRV
SweRV EH1 core
Zissi-Lei's Repositories
Zissi-Lei/dhrystone
Historical versions of Reinhold P. Weicker's Dhrystone benchmark
Zissi-Lei/ridecore
RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
Zissi-Lei/sparc64soc
OpenSPARC-based SoC
Zissi-Lei/Verilog-Automatic
Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3