Pinned Repositories
ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core
berkeley-hardfloat
circuitdiagram
A user-friendly program for making electronic circuit diagrams.
circuitdiagram-vscode
Circuit Diagram extension for Visual Studio Code.
CNN-FPGA
Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database
cnnhwpe
components
Library of components for Circuit Diagram.
core_ddr3_controller
A DDR3 memory controller in Verilog for various FPGAs
coremark
CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcrontrollers (MCU).
Cores-SweRV
SweRV EH1 core
Zissi-Lei's Repositories
Zissi-Lei/berkeley-hardfloat
Zissi-Lei/cnnhwpe
Zissi-Lei/components
Library of components for Circuit Diagram.
Zissi-Lei/ElegantBook
Elegant LaTeX Template for Books
Zissi-Lei/ElegantNote
Elegant LaTeX Template for Notes
Zissi-Lei/ElegantPaper
Elegant LaTeX Template for Working Papers
Zissi-Lei/FPGADesignElements
A self-contained online book containing a library of FPGA design modules and related coding/design guides.
Zissi-Lei/fpnew
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
Zissi-Lei/gemmini
Berkeley's Spatial Array Generator
Zissi-Lei/hwacha
Microarchitecture implementation of the decoupled vector-fetch accelerator
Zissi-Lei/Konata
Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from https://github.com/shioyadan/Konata/releases
Zissi-Lei/LogicCircuit
LogicCircuit – is free, open source educational software for designing and simulating digital logic circuits.
Zissi-Lei/manim
Animation engine for explanatory math videos
Zissi-Lei/Pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL
Zissi-Lei/RISC-V-TLM
RISC-V SystemC-TLM simulator
Zissi-Lei/riscv-vp
RISC-V Virtual Prototype
Zissi-Lei/rsd
RSD: RISC-V Out-of-Order Superscalar Processor
Zissi-Lei/rv_lib
Zissi-Lei/rvv-intrinsic-doc
RISC-V Vector Extension Intrinsic Document
Zissi-Lei/sv2v
SystemVerilog to Verilog conversion
Zissi-Lei/systemc-compiler
This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
Zissi-Lei/Tengine
Tengine is a lite, high performance, modular inference engine for embedded device
Zissi-Lei/TinyAcc
This is a project to implement a Neural Network Model with descent functionality
Zissi-Lei/tinyml
This repo is for Efinix TinyML platform, which offers end-to-end flow that facilitates TinyML solution deployment on Efinix FPGAs.
Zissi-Lei/ventus-gpgpu
GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
Zissi-Lei/verilog-axi
Verilog AXI components for FPGA implementation
Zissi-Lei/verilog-axis
Verilog AXI stream components for FPGA implementation
Zissi-Lei/verilog-perl
Verilog parser, preprocessor, and related tools for the Verilog-Perl package
Zissi-Lei/yosys
Yosys Open SYnthesis Suite
Zissi-Lei/ztachip
Opensource software/hardware platform to build edge AI solutions deployed on FPGA or custom ASIC hardware.