aanair3

aanair3's Stars

• greati/processor_risc

  A simple processor implemented in SystemC

  Language:TeX204

• dicksites/KUtrace

  Low-overhead tracing of all Linux kernel-user transitions, for serious performance analysis. Includes kernel patches, loadable module, and post-processing software. Output is HTML/SVG per-CPU-core timeline that you can pan/zoom down to the nanosecond.

  Language:HTML63260

• yuzeng2333/autoGenILA

  Automatic generation of architecture-level models for hardware from its RTL design.

  Language:Verilog122

• sld-columbia/hl5

  A 32-bit RISC-V Processor Designed with High-Level Synthesis

  Language:C4718

• secworks/sha256

  Hardware implementation of the SHA-256 cryptographic hash function

  Language:Verilog31789

• Xilinx/Vitis_Libraries

  Vitis Libraries

  Language:C++886354

• tomtor/HDL-deflate

  FPGA implementation of deflate (de)compress RFC 1950/1951

  Language:Verilog566

• kcamenzind/BluespecIntroGuide

  An introductory guide to Bluespec (BSV)

  Language:TeX5717

• Zaoldyeckk/High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS

  This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems using Vivado HLS. Now under 2018.2 version.

  Language:C50101

• bigbrett/wssha256_hls

  hardware accelerator for sha256 hash algorithm using Vivado HLS

  Language:C44

• kunpengcompute/KAEzip

  A high-performance hardware accelerator for compression/decompression algorithm library of zlib based on kunpeng processor

  Language:C1712

• robust-systems-group/illusion_system

  Repository of code & results for the Illusion Paper

  Language:C71

• makaimann/ride-core-demo

  A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core

  Language:Verilog10

• upscale-project/generic-sqed-demo

  Language:Verilog113

• opencomputeproject/Project-Zipline

  Defines a lossless compressed data format that is independent of CPU type, operating system, file system, and character set, and is suitable for compression using the XP10 algorithm.

  Language:Verilog28147

• khaled-e-a/Hardware-Software-SHA-3-HLS

  HLS SHA-3 Accelerator

  Language:C7

• tishi43/h264_decoder

  Language:Verilog219

• aiminickwong/H264

  H264视频解码verilog实现

  Language:Verilog7738

• ranjan-yadav/TMDS-encoder-8b-10b

  TMDS is a method for serially transmitting high-speed digital signals. The “transition minimized” part is realized by the 8b/10b encoding algorithm used by TMDS, which is implemented here in digital logic. This TMDS encoding is used in several digital communication interfaces, including the DVI and HDMI video interfaces. It is important to note that this TMDS encoding was created by Silicon Image in 1999 and is not the same as the original 8b/10b encoding introduced by IBM in 1983. The “differential signaling” part of the technique relates to the IO circuit and is not discussed in detail here. The TMDS encoding algorithm reduces electromagnetic emissions, achieves DC balance on the wires, and still allows for reliable clock recovery. The encoding seeks to minimize the transitions (thus reducing interference between channels) while still retaining frequent enough transitions for clock recovery. By keeping the number of ones and zeros on the line nearly equal, the DC balance part of the encoding algorithm improves the noise margin.

  Language:Verilog41

• bcattle/hardh264

  A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.

  Language:VHDL27567

• cisco/openh264

  Open Source H.264 Codec

  Language:C++5.5k1.8k

• davidrmiller/biosim4

  Biological evolution simulator

  Language:C++3.2k458

• rsnikhil/Bluespec_BSV_Tutorial

  Bluespec BSV HLHDL tutorial

  Language:Bluespec9222

• z11i/pysat

  Simple SAT solver with CDCL implemented in Python

  Language:Python145

• foolmarks/aesctr_128_hls

  AES-128 CTR mode Encryption/Decryption system for Vivado HLS

  4

• diffblue/cbmc

  C Bounded Model Checker

  Language:C++842262

• upscale-project/aqed-dac2020-results

  Source files to reproduce the results shown for A-QED at DAC 2020

  Language:C++73

• nvdla/hw

  RTL, Cmodel, and testbench for NVDLA

  Language:Verilog1.7k568

• doctor3w/HLS-Cryptography-Accelerator

  A crypto accelerator written for HLS to an FPGA that actually makes it slower than running it on your computer

  Language:Assembly163

• microideax/T-DLA

  Language:VHDL164