abejgonzalez

EECS Ph.D. Student at ADEPT Lab

University of California at BerkeleyBerkeley, California

Pinned Repositories

abejgonzalez.github.io
My personal webpage
Language:CSS1 1 00
ariane
Ariane is a 6-stage RISC-V CPU capable of booting Linux
Language:SystemVerilog10
boom-attacks
Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)
Language:C3 1 01
coremarkpro-util-make-riscv
The utility files to port CoreMark-Pro to RISC-V.
Language:Makefile00
firechip
Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.
Language:C0 1 00
firesim
FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation of RISC-V Systems (Rocket Chip, BOOM) in the Cloud
Language:Python10
icenet
Network components (NIC, Switch) for FireBox
Language:Scala00
riscv-code-constructor
Quick layout to build RISC-V baremetal binaries
Language:C3 1 11
zsim-smt
Enhancing an Out-of-Order Processor for Latency-Critical Cloud Applications
Language:C++6 4 11
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Language:Scala1.6k 85 650618

abejgonzalez's Repositories

abejgonzalez/abejgonzalez.github.io
My personal webpage
Language:CSS1 1 00
abejgonzalez/dotfiles
Configuration files for my Linux ecosystem
Language:Lua11
abejgonzalez/firesim-protoacc-sha3-ae
Language:Scala1 2 0
abejgonzalez/chipyard
Language:C
abejgonzalez/chipyard-protoacc-sha3-ae
Language:C
abejgonzalez/chisel-testers
Provides various testers for chisel users
Language:Scala
abejgonzalez/fake-subproject
abejgonzalez/firemarshal-protoacc-sha3-ae
Language:C2 0
abejgonzalez/firesim-aws-fpga-temp
Language:VHDL2 0
abejgonzalez/firesim-vitis
Language:Makefile
abejgonzalez/fleetbench
Benchmarking suite for Google workloads
Language:C++0 0
abejgonzalez/fpga-shells
Language:Scala1 0
abejgonzalez/mdb-example
Language:Shell2 0
abejgonzalez/monetdb-cluster-tpch-analysis
Language:Shell
abejgonzalez/proto-sha3-sw
Language:C++
abejgonzalez/protoacc-protoacc-sha3-ae
Language:Scala2 0
abejgonzalez/riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
Language:Scala
abejgonzalez/riscv-isa-sim
Spike, a RISC-V ISA Simulator
abejgonzalez/riscv-linux-protoacc-sha3-ae
Language:C2 0
abejgonzalez/riscv-torture-protoacc-sha3-ae
Language:Scala
abejgonzalez/rocket-chip
Rocket Chip Generator
Language:Scala1 01
abejgonzalez/rocket-chip-protoacc-sha3-ae
Language:Scala2 0
abejgonzalez/sifive-blocks
Common RTL blocks used in SiFive's projects
Language:Scala
abejgonzalez/texdocs
Language:TeX1 0
abejgonzalez/tpch-monetdb-workload
Language:Python2 0
abejgonzalez/tpch-scripts
Language:Roff2 0
abejgonzalez/ucb-bar-docs
abejgonzalez/vitis-help
Language:SystemVerilog1 0
abejgonzalez/Vitis_Accel_Examples
Vitis_Accel_Examples
Language:Makefile1 0
abejgonzalez/XRT
Xilinx Run Time for FPGA