Pinned Repositories
abejgonzalez.github.io
My personal webpage
ariane
Ariane is a 6-stage RISC-V CPU capable of booting Linux
boom-attacks
Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)
coremarkpro-util-make-riscv
The utility files to port CoreMark-Pro to RISC-V.
firechip
Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.
firesim
FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation of RISC-V Systems (Rocket Chip, BOOM) in the Cloud
icenet
Network components (NIC, Switch) for FireBox
riscv-code-constructor
Quick layout to build RISC-V baremetal binaries
zsim-smt
Enhancing an Out-of-Order Processor for Latency-Critical Cloud Applications
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
abejgonzalez's Repositories
abejgonzalez/abejgonzalez.github.io
My personal webpage
abejgonzalez/dotfiles
Configuration files for my Linux ecosystem
abejgonzalez/firesim-protoacc-sha3-ae
abejgonzalez/chipyard
abejgonzalez/chipyard-protoacc-sha3-ae
abejgonzalez/chisel-testers
Provides various testers for chisel users
abejgonzalez/fake-subproject
abejgonzalez/firemarshal-protoacc-sha3-ae
abejgonzalez/firesim-aws-fpga-temp
abejgonzalez/firesim-vitis
abejgonzalez/fleetbench
Benchmarking suite for Google workloads
abejgonzalez/fpga-shells
abejgonzalez/mdb-example
abejgonzalez/monetdb-cluster-tpch-analysis
abejgonzalez/proto-sha3-sw
abejgonzalez/protoacc-protoacc-sha3-ae
abejgonzalez/riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
abejgonzalez/riscv-isa-sim
Spike, a RISC-V ISA Simulator
abejgonzalez/riscv-linux-protoacc-sha3-ae
abejgonzalez/riscv-torture-protoacc-sha3-ae
abejgonzalez/rocket-chip
Rocket Chip Generator
abejgonzalez/rocket-chip-protoacc-sha3-ae
abejgonzalez/sifive-blocks
Common RTL blocks used in SiFive's projects
abejgonzalez/texdocs
abejgonzalez/tpch-monetdb-workload
abejgonzalez/tpch-scripts
abejgonzalez/ucb-bar-docs
abejgonzalez/vitis-help
abejgonzalez/Vitis_Accel_Examples
Vitis_Accel_Examples
abejgonzalez/XRT
Xilinx Run Time for FPGA