Pinned Repositories
bluecheck
A generic test bench written in Bluespec
bsvtokami
Translates Bluespec SystemVerilog to Kami for use with the coq proof assistant.
connectal
Connectal is a framework for software-driven hardware development.
FluteEnclavesTagging
RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
fpgamake
Generates Makefiles to synthesize, place, and route verilog using Vivado
linear-algebra-speed-tests
Multiple speed tests for basic linear algebra algorithms
ps-eye-encoder
PlayStation Eye Encoder
riscv-csrs
Specification and Tools for RISC-V Control and Status Registers
recycle-bsv-lib
Collection of BSV packages.
riscy
Riscy Processors - Open-Sourced RISC-V Processors
acw1251's Repositories
acw1251/linear-algebra-speed-tests
Multiple speed tests for basic linear algebra algorithms
acw1251/riscv-csrs
Specification and Tools for RISC-V Control and Status Registers
acw1251/bluecheck
A generic test bench written in Bluespec
acw1251/bsvtokami
Translates Bluespec SystemVerilog to Kami for use with the coq proof assistant.
acw1251/connectal
Connectal is a framework for software-driven hardware development.
acw1251/FluteEnclavesTagging
RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
acw1251/fpgamake
Generates Makefiles to synthesize, place, and route verilog using Vivado
acw1251/ps-eye-encoder
PlayStation Eye Encoder
acw1251/PiccoloEnclavesTagging
RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
acw1251/riscv-configstring-parser
Flex and Bison parser for RISC-V Configuration Strings from Privileged Spec v1.9
acw1251/riscv-isa-sim
Spike, a RISC-V ISA Simulator
acw1251/riscv-semantics
acw1251/TatSu
竜 TatSu generates Python parsers from grammars in a variation of EBNF
acw1251/yosys
Yosys Open SYnthesis Suite
acw1251/z3
The Z3 Theorem Prover