Pinned Repositories
fifo_module
logicgates
multi-cycle-cpu
opencv-freecodecamp
Learn OpenCV in 4 Hours - Code used in my Python and OpenCV course on freeCodeCamp.
opencv_tutorials
pihole
rebek-007
riscvisa_ifu
uvm_riscv
verilog_codes
adideb-das's Repositories
adideb-das/riscvisa_ifu
adideb-das/verilog_codes
adideb-das/fifo_module
adideb-das/logicgates
adideb-das/multi-cycle-cpu
adideb-das/opencv-freecodecamp
Learn OpenCV in 4 Hours - Code used in my Python and OpenCV course on freeCodeCamp.
adideb-das/opencv_tutorials
adideb-das/pihole
adideb-das/rebek-007
adideb-das/uvm_riscv
adideb-das/remote-controlled-car
adideb-das/riscv-based-cpu
adideb-das/RISCV_CPU
32 bit Base RISCV Simulator
adideb-das/riscv_cpu_core
adideb-das/riscv_model1
adideb-das/riscv_uvm
adideb-das/Sailing-Downstream
This repository is used for the coding task "Sailing Downstream"
adideb-das/scoppy
Use your Rasperry Pi Pico and Android Phone as an Oscilloscope and Logic Analyzer
adideb-das/scoppyproject
adideb-das/simple_dual_port_ram
adideb-das/single_cycle_cpu
adideb-das/smitrv
An implementation of RISC-V based core from SMIT
adideb-das/vlsi_soc_verilog
Created this repository with reference to VLSI SoC Design using Verilog HDL by Maven Silicon