VLSI SoC Design using Verilog HDL

I have completed the course VLSI SoC Design using Verilog HDL from Maven Silicon. https://elearn.maven-silicon.com/course/VLSISoCDesignusingVerilogHDL-35

Deployment

To deploy this project clone this github repository and extract the files to VS Code.

Navigate to the particular folder and open a new terminal window

  iverilog -o sim xxx_tb.v

where sim is the simulation output and xxx is either of the seven logic gates.

A simulation output of sim is created as the output file . To generate the timing diagram of sim , enter

vvp sim

A timing diagram of xxx_waveform.vcd will be generated as timing diagram file. We can view it in GTKWave using the following command

gtkwave xxx_waveform.vcd

A timing diagram will be generated by GTKwave Analyser. We can analyse the output signals as per our requirement.