adithyapi

adithyapi's Stars

• nishit0072e/RTL-to-GDSII

  Complete installation flow of yosys, OpenSTA and OpenROAD for RTL Verification, Synthesis, Timing Analysis, Power Analysis & GDSII layout generation

  Language:C++7

• seanpm2001/Learn-Verilog-AMS

  A repository for showcasing my knowledge of the Verilog AMS programming language, and continuing to learn the language.

  Language:Verilog31

• microchip-pic-avr-examples/pic18f16q20-i3c-getting-started-mplab-mcc

  This code example demonstrates the different features of I3C Target module such as Hot-Join (HJ), Private Transaction, In-Band Interrupt (IBI), Reset and Common Code Command (CCC). Other compatible PIC18-Q20 family of MCUs are: PIC18F06Q20

  Language:C2

• mabrains/i2c_skywater_130nm

  I2C implementation on Skywater 130nm

  Language:Verilog1

• RadhaKulkarni26/Design-and-Implementation-of-a-Mixed-Signal-Circuit-of-Multiplexer

  In this repository, i have explained what are Mixed Signal Circuits and how to design and implement it using eSim and Makerchip Softwares

  Language:Verilog1

• RadhaKulkarni26/Design-and-Implementation-of-2-1-MUX-using-sky130-PDK

  1

• RadhaKulkarni26/Design-and-Implementation-of-Full-Adder-using-sky130-PDK

  11

• iic-jku/SKY130_SAR-ADC1

  Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license

  Language:Verilog386

• AsFigo/apb_uvc_verilator

  APB UVC ported to Verilator

  Language:SystemVerilog113

• verilator/verilator-announce

  Announcements related to Verilator

  383

• shubhi704/APB-Protocol

  Language:Verilog3812

• RikPi/riscv-based-myth

  Repository of the course RISC-V Based Myth I followed in September 2023

  Language:TL-Verilog1

• AsFigo/pyslint

  SystemVerilog Linter based on pyslang

  Language:SystemVerilog2324

• IHP-GmbH/IHP-Open-PDK

  130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design

  Language:HTML43367

• aisichenko/gdsfactory-workshop-ucsb

  Language:Jupyter Notebook102

• iic-jku/IIC-OSIC-TOOLS

  IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.

  Language:Python37369

• aolofsson/awesome-opensource-hardware

  List of awesome open source hardware tools, generators, and reusable designs

  Language:Python1.9k182

• lnis-uofu/SOFA

  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA

  Language:Verilog13428

• The-OpenROAD-Project/OpenROAD-flow-scripts

  OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

  Language:Verilog363294

• The-OpenROAD-Project/OpenROAD

  OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

  Language:Verilog1.7k579

• prajwalgekkouga/AHB-to-APB-Bridge

  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.

  Language:Verilog5214

• snbk001/100DaysofRTL

  100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore

  Language:SystemVerilog303

• phani91/Vams

  Verilog AMS

  21

• POSH-Emulation/SPICE-conversion

  Abstraction of RNM from SPICE netlist

  Language:HTML2

• POSH-Emulation/AMS-assertions

  Extensions to System Verilog to support AMS assertions

  4

• damnsavage/analog_models

  Wreal models of analog circuit components (verilog ams)

  Language:Verilog83

• muhammadaldacher/Modeling-of-4-bit-Flash-ADC-and-4-bit-DAC

  This project shows how to model a 4-bit flash ADC and a 4-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 4-bit ADC based on the flash architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.

  Language:MATLAB125

• muhammadaldacher/Modeling-of-10-bit-Pipeline-ADC-and-10-bit-DAC

  This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 10-bit ADC based on 1-bit per stage pipelined architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.

  Language:MATLAB2212

• subramaniantr/verilogAMS

  Language:Verilog51

• ColsonZhang/VerilogA-Wave-Generator

  The codes are used to generate the VerilogA code which can be directly used in the spectre simulation .The generated VerilogA code's fuction is to generate the specific waveforms according to your setting.And the setting is done in the python code (main.py), which will facilitate greatly the coding works.

  Language:Python4414