adithyasunil26/basejump_stl_alu
Core created as a proof of concept for BaseJump STL integration into FuseSoC. Simple ALU with an SRAM generated by bsg_fakeram.
Verilog
No issues in this repository yet.
Core created as a proof of concept for BaseJump STL integration into FuseSoC. Simple ALU with an SRAM generated by bsg_fakeram.
Verilog
No issues in this repository yet.