Pinned Repositories
2.87GHz-MWG-MPW5
2.87 GHz microwave signal generator in SKY130
Active-Noise-Control
Implementing and analyzing various active noise control algorithms.
Carry-Lookahead-Adder
4-bit Carry Lookahead Adder - RTL implementation in Verilog, SPICE netlist and MAGIC layouts
CCIoT-Not-A-Helmet
IoT system with dashboard for monitoring working conditions in mines and alerting workers in emergencies.
CMOS-Digital-Design
Files from CMOS Digital Design Tutorials
CMOS-frequency-synthesizer-SKY130
GSoC-21-Project-Report
Final report for Google Summer of Code 2021 project 'Porting BaseJump STL to FuseSoC' under FOSSi Foundation.
NewsScraper
riscvy
5 stage pipelined RISC-V processor with forwarding, stalling and flushing
Y86-64-Processor
A Y86-64 processor implemented using Verilog
adithyasunil26's Repositories
adithyasunil26/2.87GHz-MWG-MPW5
2.87 GHz microwave signal generator in SKY130
adithyasunil26/CMOS-Digital-Design
Files from CMOS Digital Design Tutorials
adithyasunil26/CCIoT-Not-A-Helmet
IoT system with dashboard for monitoring working conditions in mines and alerting workers in emergencies.
adithyasunil26/CMOS-frequency-synthesizer-SKY130
adithyasunil26/homebrew-cask
🍻 A CLI workflow for the administration of macOS applications distributed as binaries
adithyasunil26/Open-MPW-shuttle-guide
adithyasunil26/riscvy
5 stage pipelined RISC-V processor with forwarding, stalling and flushing
adithyasunil26/TAP-Controller
adithyasunil26/basejump_stl_alu
Core created as a proof of concept for BaseJump STL integration into FuseSoC. Simple ALU with an SRAM generated by bsg_fakeram.
adithyasunil26/basejump_stl_cores
FuseSoC cores for BaseJumpSTL
adithyasunil26/Leakage-current-DVD
adithyasunil26/2-stage-OTA
adithyasunil26/2.87GHz-MWG-SKY130
adithyasunil26/adithyasunil26
adithyasunil26/adithyasunil26.github.io
adithyasunil26/basejump_stl
BaseJump STL: A Standard Template Library for SystemVerilog
adithyasunil26/bsg_fakeram_generator
FuseSoC generator for BSG fakeram generator
adithyasunil26/DVD-Project-1
adithyasunil26/Fusesoc-Parameter-Sweeper
Sweeping parameters for a FuseSoC target
adithyasunil26/homebrew-cask-bump
Python script to run livecheck and bump-cask-pr for new versions of casks
adithyasunil26/homebrew-formula-bump
Python script to run livecheck and bump-formula-pr for new versions of formulas
adithyasunil26/IPA-Project
adithyasunil26/LID-Excitation-Features
adithyasunil26/OpenFASOC
Fully Open Source FASOC generators built on top of open-source EDA tools
adithyasunil26/Ring_oscillator_sky130
https://caravel-user-project.readthedocs.io
adithyasunil26/skywater_pdk
adithyasunil26/sscs-ose-code-a-chip.github.io
IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)
adithyasunil26/ubisoft-laforge-daft-exprt
PyTorch Implementation of Daft-Exprt: Robust Prosody Transfer Across Speakers for Expressive Speech Synthesis
adithyasunil26/VCO-MPW-5
adithyasunil26/xschem
A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.