Pinned Repositories
16-bit-ALU
a-32-bit-single-cycle-microarchitecture-MIPS-processor-based-on-Harvard-Architecture.
In this project, you are required to implement a 32-bit single-cycle microarchitecture MIPS processor based on Harvard Architecture. The single-cycle microarchitecture executes an entire instruction in one cycle. In other words instruction fetch, instruction decode, execute, write back, and program counter update occurs within a single clock cycle.
a-Pipelined-32-bit-MIPS-processor-based-on-Harvard-Architecture.-
A Pipelined 32-bit microarchitecture MIPS processor based on Harvard Architecture with hazard handling both data and control hazards.
Cache-Controller-Implementation-with-Write-Through-Policy-
In this project, we will work on implementing a simple caching system for the RISC-V processor. For simplicity, we will integrate the caching system with the single-cycle implementation.
Generic-Clock-Divider
A clock divider is a circuit that takes an input signal of a frequency fin and generates an output signal of a frequency fout, where fout = fin / n and ''n'' is an integer
N-bit-integer-multiplier-and-divider-using-VHDL
RTL-to-GDS-Implementation-of-Low-Power-Configurable-Multi-Clock-Digital-System
(the final project of Digital IC Design Diploma (Under the supervision of Eng. Ali El- Temsah)
UART-USB-bus-reference-model-using-MATLAB
ELC-4028-NN
Projects of Deep Learning and Neural Networks applications course in 4th year
ahmed-elhoseiny's Repositories
ahmed-elhoseiny/a-Pipelined-32-bit-MIPS-processor-based-on-Harvard-Architecture.-
A Pipelined 32-bit microarchitecture MIPS processor based on Harvard Architecture with hazard handling both data and control hazards.
ahmed-elhoseiny/16-bit-ALU
ahmed-elhoseiny/a-32-bit-single-cycle-microarchitecture-MIPS-processor-based-on-Harvard-Architecture.
In this project, you are required to implement a 32-bit single-cycle microarchitecture MIPS processor based on Harvard Architecture. The single-cycle microarchitecture executes an entire instruction in one cycle. In other words instruction fetch, instruction decode, execute, write back, and program counter update occurs within a single clock cycle.
ahmed-elhoseiny/UART-USB-bus-reference-model-using-MATLAB
ahmed-elhoseiny/Cache-Controller-Implementation-with-Write-Through-Policy-
In this project, we will work on implementing a simple caching system for the RISC-V processor. For simplicity, we will integrate the caching system with the single-cycle implementation.
ahmed-elhoseiny/Generic-Clock-Divider
A clock divider is a circuit that takes an input signal of a frequency fin and generates an output signal of a frequency fout, where fout = fin / n and ''n'' is an integer
ahmed-elhoseiny/N-bit-integer-multiplier-and-divider-using-VHDL
ahmed-elhoseiny/RTL-to-GDS-Implementation-of-Low-Power-Configurable-Multi-Clock-Digital-System
(the final project of Digital IC Design Diploma (Under the supervision of Eng. Ali El- Temsah)