In this project, you are required to implement a 32-bit single-cycle microarchitecture MIPS processor based on Harvard Architecture. The single-cycle microarchitecture executes an entire instruction in one cycle. In other words instruction fetch, instruction decode, execute, write back, and program counter update occurs within a single clock cycle.
Objective
Referring to figure one, you are required to write the RTL Verilog files for all sub-
modules of the MIPS processor (e.g. Register File, Instruction Memory, etc.). Then,
implementing the top module of the MIPS processor.
Top Module View
The processor is composed of a datapath and a controller. The controller, in turn, is
composed of the main decoder and the ALU decoder. Figure 2 shows a block diagram of the
single-cycle MIPS processor interfaced to external memories.
Main Modules
- a 32-bit ALU 4) Register File
- Program Counter 5) Data Memory
- Instruction memory 6) Control Unit
Small Modules
- Sign Extend 3. Adder
- shift_left_twice 4. MUX
for more details, go to and read "Final Project" to learn more about the specifications of the design
Program 1: GCD of 120 and 180
Program 2: Factorial Number of 7
Program 3: fibonacci sequence
