/Signal-Processing-EEG

Academic Lab Course of the 27th batch of Computer Science & Engineering | University of Rajshahi - 🇧🇩

Primary LanguageVerilog

Digital System Design Lab

Language

  • Verilog - a Hardware Description Language used to model electronic systems

Lab Tasks

  • Binary Adder & Subtractor ✓
  • Binary Ripple Counter ✓
  • Full Adder ✓
  • Half Adder ✓
  • Jk Flip Flop ✓
  • Mod 10 Counter ✓
  • Ripple Adder ✓
  • Sequence Counter ✓
  • Up & Down Counter ✓