aidachui

aidachui's Stars

• hizbi-github/AXI4_Master_Interconnect_Slave

  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple masters arbitration. Simulation waveforms are also included.

  Language:Verilog305

• freecores/xge_mac

  Ethernet 10GE MAC

  Language:Verilog4524

• alexforencich/verilog-ethernet

  Verilog Ethernet components for FPGA implementation

  Language:Verilog2.4k716

• fpgadeveloper/sfp28-fmc-xxv

  10G/25G Ethernet reference designs for the Opsero Quad SFP28 FMC (OP081)

  Language:Tcl11

• RichardYJ/PIC_TEST

  Test PIC and ACC_100G_QSFP28 or ACC_100G_SFP28 by write register

  Language:C22

• www-asics-ws/usb2_dev

  USB 2.0 Device IP Core

  Language:Verilog5325

• Barkhausen-Institut/usrp_uhd_wrapper

  This repo wraps the Universal Hardware Driver for accessing the USRP X410 for easier use of burst-based use-cases.

  Language:Python4

• chunter18/HLS-MLP

  Multilayer Perceptron in Vivado HLS targeting Kintex7 FPGA.

  Language:Ada4

• hassyy/mlp_hls

  Multi Layer Perceptron by Vivado HLS for Xilinx FPGA implementation

  Language:C++111

• walkieq/RNN_HLS

  An LSTM template and a few examples using Vivado HLS

  Language:C4312

• caichao/parchar

  A resource-efficient and calibration-efforts free TDC using parallel short chains

  2

• ZzzzzzS/FPGA_DDS

  使用FPGA进行直接数字合成DDS

  Language:Verilog31

• ATaylorCEngFIET/MZ_402_PID_HLS

  PID HLS Implementation

  Language:VHDL101

• shuji-oh/Tapped_Delay_TDC

  Language:Verilog11

• tsheaves/tiny_tapeout_tdc

  Language:Verilog1

• EveRYouNg-OranGe/TDC-on-FPGA

  A TDC design based on Anlogic EG4 FPGA

  Language:Verilog31

• kristianpaul/tdc-core

  tdc core from ohwr with an small milkymist soc

  Language:Verilog21

• cdrewes/Tunable-TDC

  Language:Verilog1

• FoRTE-Research/TDC2

  Language:VHDL2

• xiguazaitortoise/tdc

  Language:Verilog21

• iic-jku/jku-tt06-tdc-v1

  TDC based on simple inverter chain

  Language:Verilog43

• enggsajjad/TDCTester

  Time to Digital Converter TDC Tester based on Microcontroller and FPGA

  Language:Verilog51

• icebai-ustc/TDC

  Time to digital converter implemented on a Cyclone V (DE10-Nano) FPGA.

  91

• nancyjlau/CSE125-Final-Project

  This project implements a simple tapped delay line TDC.

  Language:Verilog31

• shuji-oh/PLI_TDC_for_CAN

  "PLI-TDC: Super Fine Delay-Time Based Physical-Layer Identification with Time-to-Digital Converter for In-Vehicle Networks" ACM ASIACCS 2021

  Language:Verilog102

• LGG1997/FPGA_TDC_1_0

  Language:Verilog101

• PranavGovekar/tdcOnFPGA

  Implementation of tappped delay line TDC on FPGA

  Language:Verilog133

• Sidharth224/TDL-TDC

  Language:Verilog1

• lulf0020/Behavior-modeling-of-PLL

  MathWorks-Excellence-in-Innovation/projects/Behavioral Modelling of Phase-Locked Loop using Deep Learning Techniques/

  Language:MATLAB7

• filipamator/adpll

  All digital PLL

  Language:VHDL265