ajayvreddy

I love this world. "Hello World!"

India

Pinned Repositories

Caught
Caught the bug.
00
conf_files
configuration files such as vimrc, tmux etc
Language:Vim Script0 1 00
ISG
Random instruction generator for RISC-V processor verification
Language:Python0 0 00
RiscGen
Generator of RISCV assembly
0 1 00
whisper
Language:C++00
riscv-isa-sim
Spike, a RISC-V ISA Simulator
Language:C2.5k 131 872878

ajayvreddy's Repositories

ajayvreddy/Caught
Caught the bug.
00
ajayvreddy/conf_files
configuration files such as vimrc, tmux etc
Language:Vim Script0 1 00
ajayvreddy/ISG
Random instruction generator for RISC-V processor verification
Language:Python0 0 00
ajayvreddy/RiscGen
Generator of RISCV assembly
0 1 00
ajayvreddy/whisper
Language:C++00