Note
The version implemented here is v1.0.0-38-g865e7a7. The spec pdf is present in docs/bitmanip-1.0.0-38-g865e7a7.pdf.
The repo structure is as follows:
bbox.bsv - The top module of the design. Has the interface definition and module definition which calls the BitManip calculation.
Makefile
src/ - The bluespec design, implementing the BitManip Extension.
compute.bsv - The top function which selects between the functions implemented for the spec depending on the instruction.
bbox.defines - Has the macro definitions used to match and select between the instructions.
bbox_types.bsv - The types, structures, enum, macros used in the design are defined here.
Zba.bsv - Contains the functions implementing all the instructions (8) that are a part of the Zba sub-extension.
Zbb.bsv - Contains the functions implementing all the instructions (24) that are a part of the Zbb sub-extension.
Zbc.bsv - Contains the functions implementing all the instructions (3) that are a part of the Zbc sub-extension.
Zbs.bsv - Contains the functions implementing all the instructions (8) that are a part of the Zbs sub-extension.
bbox_verif/ - The directory where the scripts required for running the cocotb tests are present.
test_bbox.py - This file consists of a cocotb testbench for bbox dut.
bbox_ref_model.py - This file consists reference model which used in verifying the design (DUT).
instr_fmt.py - This file is consists a function that randomizes the wildcard bits in each instruction to generate random test vectors for each instruction.
ref_model_impl.py - This file consists of functions that implement each instruction found in the spec.
docs/ - The specification and other miscellaneous docs.
Steps to run:
Note Change BSCDEFINES macro in Makefile to RV64 or RV32 according to use. Also change base in bbox_verif/test_bbox.py to RV64 or RV32.
To just generate the verilog: make generate_verilog
To simulate: make sim
To generate verilog and simulate: make simulate
To clean the build: make clean_build
Design choices
All reference python implementations in bbox_verif/ref_model_impl.py have same function prototype to be uniform. If there is no rs2 requirement in the instruction, the corresponding data - instr or shamt is passed to the function via rs2.
The verification testbench generates 10 random test cases for each instruction on each run, to make the testbench easily catch corner cases (if any).