Pinned Repositories
Arduino
open-source electronics prototyping platform
ariane
Ariane is a 6-stage RISC-V CPU
awesome-courses
:books: List of awesome university courses for learning Computer Science!
BrookGPU
The original Stanford Code befor becomming Brook Plus - pulled from Subversion 1889
Cache
Verilog Cache-4Ways IP development
FloatPointArithmetic
Float Point Add, Multiply and Division.
Mac
Memory Access Controller handles the actual bank, row, col sram request
MipsCpu
A six pipelined (Fetch, Decode, Issue, Execute, Memory, WriteBack) cpu that only implements parts of mips instructions in Verilog
RISCV
VerilogHDL version superscale RV32&64, may consider the vector operation
wishbone_uvc
Wishbone protocol open source universal verification component (UVC). It is easy to be used in UVM verification environment for opencpu.
alexzhang007's Repositories
alexzhang007/FloatPointArithmetic
Float Point Add, Multiply and Division.
alexzhang007/wishbone_uvc
Wishbone protocol open source universal verification component (UVC). It is easy to be used in UVM verification environment for opencpu.
alexzhang007/RISCV
VerilogHDL version superscale RV32&64, may consider the vector operation
alexzhang007/Arduino
open-source electronics prototyping platform
alexzhang007/ariane
Ariane is a 6-stage RISC-V CPU
alexzhang007/awesome-courses
:books: List of awesome university courses for learning Computer Science!
alexzhang007/BrookGPU
The original Stanford Code befor becomming Brook Plus - pulled from Subversion 1889
alexzhang007/CNTK
Microsoft Cognitive Toolkit (CNTK), an open source deep-learning toolkit
alexzhang007/ConvNetAsic
alexzhang007/Cores-SweRV
SweRV EH1 core
alexzhang007/darknet
Convolutional Neural Networks
alexzhang007/DRAMSim2
DRAMSim2: A cycle accurate DRAM simulator
alexzhang007/e200_opensource
The Ultra-Low Power RISC Core
alexzhang007/lizard
Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
alexzhang007/MCGSim
Linux version of the simulation where it provide the MS solution in http://cs.lth.se/eda075/lectures/
alexzhang007/minerva
A 32-bit RISC-V soft processor
alexzhang007/MipsSimulator
Mips CPU binary code simulator with C++ code in cycle model
alexzhang007/ModelFactory
A Matlab/Octave toolbox to create human body models
alexzhang007/OpenCNN
Open Convolution Core
alexzhang007/OpenSoCFabric
OpenSoC Fabric - A Network-On-Chip Generator
alexzhang007/Parser-Verilog
A Standalone Structural Verilog Parser
alexzhang007/RiscGpu
RISC GPU
alexzhang007/riscv-isa-sim
Spike, a RISC-V ISA Simulator
alexzhang007/sha3
FIPS 202 compliant SHA-3 core in Verilog
alexzhang007/SoC-Design-DDR3-Controller
DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
alexzhang007/tensorflow
An Open Source Machine Learning Framework for Everyone
alexzhang007/Verilog-Quadrature-Decoder-I2C-Slave
Verilog Quadrature Decoder with I2C slave to retrieve counts and reset counters
alexzhang007/VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
alexzhang007/vscale
Verilog version of Z-scale (deprecated)
alexzhang007/WECB-VZ-GPL