1. Naming style
1.a wire variable is prefix with w*. (Hungarian notation)
1.b reg variable is prefix with r*. (Hungarian notation)
1.c pipeline variable is prefix with A_B_pp*, A is the previous stage name; while B is the next stage name.(Hungarian notation for pipeline+Camel notation)
1.d variable is general [w|r]AbcDef (Hungarian notation + Pascal notation), but it might be longer, use the abbrevationn: wAD_Ghi since wADGhi is something confusing, A is abbr. of Abc D is abbr. of Def. Ghi is orignal name. (Pascal acronym_Pascal notation)
1.e module define is with module rounding_hardware() ; endmodule (Camel notation)
1.f module instant is with rounding_hardware RHW_0 (Pascal acronym notation_number )
Hungarian notation: m_dataProcess or mDataProcess.
Camel notation : dataProcess or data_process
Pascal notation : DataProcess
Pascal acronym notation : DP_Function()
2. Verification
2.a Unsigned float point add with same exponent.
2.b Unsigned float point add with different exponent (>23).
2.c Signed float point add which changing to substract.
3. Features
3.a Float point add operation
Status: RTL is done and verified.
Description: Float point add cannot be pipelined since it needs time to shift.
3.b Float point multiply operation
Status: RTL is done and verified and bugs are fixed (May.28.2014). Pipelined is achieved.
3.c Float point divide operation
Status: RTL is done (May.30.2014) and not verified(Jun.3.2014).
4. Architectures
