Pinned Repositories
100DaysOfRTL
100 Days of RTL
AES-128
Single pipeline AES 128 bit encryption using S-box as Look up table.
Algorithm
Algorithm
Algorithms
aneels3.github.io
cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
ECEproj
pyvsc
Python packages providing a library for Verification Stimulus and Coverage
verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.
riscv-dv
Random instruction generator for RISC-V processor verification
aneels3's Repositories
aneels3/Algorithm
Algorithm
aneels3/AES-128
Single pipeline AES 128 bit encryption using S-box as Look up table.
aneels3/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
aneels3/ECEproj
aneels3/100DaysOfRTL
100 Days of RTL
aneels3/Algorithms
aneels3/aneels3.github.io
aneels3/pyvsc
Python packages providing a library for Verification Stimulus and Coverage
aneels3/verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.
aneels3/aneels3
aneels3/awesome-open-hardware-verification
A List of Free and Open Source Hardware Verification Tools and Frameworks
aneels3/checkstyle
Checkstyle is a development tool to help programmers write Java code that adheres to a coding standard. By default it supports the Google Java Style Guide and Sun Code Conventions, but is highly configurable. It can be invoked with an ANT task and a command line program.
aneels3/digilent-xdc
A collection of Master XDC files for Digilent FPGA and Zynq boards.
aneels3/first-demo
For practice git and GitHub
aneels3/GNU-time
A modified version of GNU time that supports option to pass in STDIN, STDERR, and STDOUT to the command. It also supports option to provide a timeout duration for the command.
aneels3/hdl
HDL libraries and projects
aneels3/ide-backend
This repository contains backend API code for CTFHUB IDE.
aneels3/ide-taskmaster
The taskmaster is a component of Online IDE and Compiler project which processes the code execution tasks.
aneels3/ide-workers
aneels3/Java-Codes
aneels3/koss-sikkim-workshop
Issue list for KOSS sikkim workshop
aneels3/LaTeX-CV-Template
Simple Resume made using LaTex.
aneels3/riscv-dv
SV/UVM based instruction generator for RISC-V processor verification
aneels3/riscv-software-list
The RISC-V software tools list, as seen on riscv.org
aneels3/sandbox
aneels3/uvm-python
UVM 1.2 port to Python
aneels3/verilator
Verilator open-source SystemVerilog simulator and lint system
aneels3/workshop
Sample repository