anhducdinh/100DaysofRTL

100DaysofRTL: basic logic gates, mux, half and full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector with Moore, Edge Detector with Mealy

SystemVerilog