CSR Memory map

[kabrodzki]

Hey, could you provide some description(memory map) for the CSR?
In tests we can see some cryptic numbers:
DMAFull.scala

  axil_master.writePush(0x10, 0)
  axil_master.writePush(0x14, width)
  axil_master.writePush(0x18, height)
  axil_master.writePush(0x1c, 0)

  axil_master.writePush(0x20, height * width * 4 + width * 2)
  axil_master.writePush(0x24, width)
  axil_master.writePush(0x28, height)
  axil_master.writePush(0x2c, width)

[piotr-binkowski]

Current register map looks like this:

• 0x00 control register
• 0x04 status register
• 0x08 interrupt mask regiser
• 0x0c interrupt status register
• 0x10 reader start address
• 0x14 reader line length
• 0x18 reader line count
• 0x1c reader stride between lines
• 0x20 writer start address
• 0x24 writer line length
• 0x28 writer line count
• 0x2c writer stride between lines

You can also check WorkerCSRWrapper as that is where CSRs are connected to DMA logic ie. io.csr(0) refers to CSR at 0x00, io.csr(1) to 0x04 etc.

[kgugala]

@piotr-binkowski can you add this info to the repository? e.g. add a section in the readme