antmicro/fastvdma

Issues

• will fastvdma support tilelink directly？

  #23 opened 8 months ago by SpinEch0
  2

• Any example design in Vivado?

  #21 opened a year ago by nuclearrambo
  1

• To enable MM2S channel, need to know configurations

  #20 opened 2 years ago by kushalc2021
  1

• Getting error wile running "make test/testall" in master branch

  #19 opened 2 years ago by kushalc2021
  3

• Documentation for use as AXI4 Stream target

  #18 opened 2 years ago by p-owens
  5

• Nit: plural of bus is buses

  #17 opened 3 years ago by hughperkins
  0

• Trying to change read interface to AXI4, getting elaboration errors when generating verilog

  #14 opened 4 years ago by seandextercrevinn
  2

• Documentation for the CSR fields?

  #12 opened 4 years ago by seandextercrevinn
  1

• Is fastvdma tested on rocketchip?

  #2 opened 5 years ago by meton-robean
  1

• CSR Memory map

  #4 opened 4 years ago by kabrodzki
  2

• Could use a better name

  #1 opened 5 years ago by mithro
  1