arhamhashmi01
Computer System Engineering Student | Research Trainee @ MERL | RICS-V | Verilog | System Verilog | Python
Micro Electronic Research LabKarachi,Pakistan
Pinned Repositories
Apartment-Management-System
Apartment Management System is a Desktop Application developed using Python/Tkinter and mysql database.
arhamhashmi01
Axi4-lite
This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.
Bank-Management-System
"Bank Management System: This repository contains a C++ implementation for managing bank operations, including account management, transactions, and user authentication."
CPU-Scheduling-Algorithm
This repository contain the implementation of CPU scheduling algorithm FCFS , SJF , PRIORITY , ROUND ROBIN in python
openlane-verification
This repository offers a compact design verification flow using OpenLANE. Scripts cover synthesis correctness, functional and power verification, DRC/LVS, timing analysis, and reliability checks. Contributions are welcome.
RTL_Practice
This repository contain basic verilog codes which include the implementation of DLD (digital logic desgin ) circuits.
rv32i-pipeline-processor
This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog
rv32i-sv
This repository contain the implementation of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on System Verilog
RV32I_Single_Cycle
This repository contains the implementation of single cycle processor based on RISC-V ISA and implemented on "LOGISIM".
arhamhashmi01's Repositories
arhamhashmi01/rv32i-pipeline-processor
This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog
arhamhashmi01/RV32I_Single_Cycle
This repository contains the implementation of single cycle processor based on RISC-V ISA and implemented on "LOGISIM".
arhamhashmi01/CPU-Scheduling-Algorithm
This repository contain the implementation of CPU scheduling algorithm FCFS , SJF , PRIORITY , ROUND ROBIN in python
arhamhashmi01/rv32i-sv
This repository contain the implementation of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on System Verilog
arhamhashmi01/Apartment-Management-System
Apartment Management System is a Desktop Application developed using Python/Tkinter and mysql database.
arhamhashmi01/arhamhashmi01
arhamhashmi01/Axi4-lite
This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.
arhamhashmi01/Bank-Management-System
"Bank Management System: This repository contains a C++ implementation for managing bank operations, including account management, transactions, and user authentication."
arhamhashmi01/openlane-verification
This repository offers a compact design verification flow using OpenLANE. Scripts cover synthesis correctness, functional and power verification, DRC/LVS, timing analysis, and reliability checks. Contributions are welcome.
arhamhashmi01/RTL_Practice
This repository contain basic verilog codes which include the implementation of DLD (digital logic desgin ) circuits.
arhamhashmi01/verilog_practice
arhamhashmi01/ariane
Ariane is a 6-stage RISC-V CPU RV64-GC
arhamhashmi01/Buraq-mini-sv
This repository is the contain systemverilog version of Buraq-mini with a seperate branch for veriloator team.
arhamhashmi01/FPGA-Practice
This repository contains an extensive learning journey of FPGA
arhamhashmi01/openpiton
The OpenPiton Platform
arhamhashmi01/piton-linux
Linux Kernel for OpenPiton
arhamhashmi01/sv-practice
This repository contains an extensive learning journey of SystemVerilog, exercises and projects to enhance the understanding and proficiency in the hardware description language