There has been a substantial growth in the use of open-source technologies for hardware design over the past few years. The 2020 release of the open-source, manufacturable Skywater 130nm process node made it possible to design and manufacture a chip using entirely open-source tools. Since then, there have been over 400 chips designed and manufactured on these open-source process nodes.
This provides an interesting educational opportunity for introducing students to chip design in a low-stakes environment, without the overhead of NDAs and complex software stacks. A student only needs a baseline level of digital logic design knowledge to hit the ground running and start exploring how to prepare a simple design for fabrication. They can use interactive Jupyter notebooks to configure and understand each step of the design flow, resulting in a GDS file which they can then submit to be manufactured.
In Spring 2023, we started a new course in the CMU Electrical & Computer Engineering department: "18-224 Intro to Open Source Chip Design". The course was developed and taught by Anish Singhani, advised by Prof. Bill Nace. This course is intended to be accessible to students from a wide variety of backgrounds, and get them interested in chip design, to help them decide whether they intend to pursue further study in the space (such as by taking graduate-level coursework in the space, and/or by getting involved in research projects).
Additionally, by culminating the course in a project where students actually tape out a design and get it manufactured, students get the excitement and satisfaction of having something they can hold in their hand and say "I made this".
The first iteration of the course was a resounding success. Students were given a designated amount of area (roughly equivalent to 4000 standard cells) on the chip and had the option of using Verilog or a schematic editor. They then used the OpenLane flow to complete physical layout. We then took the submitted student designs and multiplexed them onto a single die, which we sent to Skywater for manufacturing through the ChipIgnite shuttle program.
Students developed a wide variety of projects ranging from games to CPUs to accelerators. Following are the projects designed by students (this includes both the Spring 2023 18-224 course as well as the experimental workshop version of this course taught in Fall 2022).
| Index | Project | Student | Link |
|---|---|---|---|
| 1 | 6-Bit Combinational Adder | (demo) | d01_example_adder |
| 2 | 12-Bit Counter | (demo) | d02_example_counter |
| 3 | "Beep Boop" Traffic Light Controller | (demo) | d03_example_beepboop |
| 4 | AES-128 Side-Channel Model | (demo) | d04_example_aes128sca |
| 5 | Tapeout Meta-Info | (demo) | d05_meta_info |
| 6 | Pong Game with VGA | (demo) | d06_demo_vgapong |
| 7 | Endless Runner Game with VGA | (demo) | d07_demo_vgarunner |
| 10 | Tic-Tac-Toe Game | Wahib Abib | d10_wabib_tictactoe |
| 11 | Brainfuck CPU | Gary Bailey | d11_gbailey_bfchip |
| 12 | I2C Peripheral | Owen Ball | d12_oball_i2c |
| 13 | S444 FPGA Logic Cell | Jack Duvall | d13_jrduvall_s444 |
| 14 | Traffic Light Controller | Jessie Fan | d14_jessief_trafficlight |
| 15 | Pseudo Random Number Generator | Jerry Feng | d15_jerryfen_prng |
| 16 | Digital Phase Locked Loop | Joel Gonzalez | d16_bgonzale_pll |
| 17 | Tetris Game | Navod Jayawardhane | d17_njayawar_tetris |
| 18 | Multiply-Accumulate Unit | Nikhil Dinkar Joshi | d18_nikhildj_mac |
| 19 | Encryption Unit (custom cipher) | Roman Kapur | d19_rdkapur_encryptor |
| 20 | Simplified Tetris Game | Rashi Kejriwal | d20_rashik_tetris |
| 21 | Motor Controller | Varun Kumar | d21_varunk2_motorctrl |
| 22 | Convolution Accelerator | Yushuang Liu | d22_yushuanl_convolution |
| 23 | Turing Machine | Ying Meng | d23_zhiyingm_turing |
| 24 | Tensor Processing Unit | M Nguyen | d24_mnguyen2_tpu |
| 25 | Huffman Encoder | Anusha Raghavendra | d25_araghave_huffman |
| 26 | Trainable Perceptron | Christopher Stange | d26_cjstange_perceptron |
| 27 | Floating Point Unit | Sri Lakshmi Vemulapalli | d27_svemulap_fpu |
| 28 | Microcoded CPU | Ganesh Venkatachalam | d28_gvenkata_ucpu |
| 29 | Intel 8008-based CPU | Brendan Wilhelm | d29_bwilhelm_i8008 |
| 30 | Tiny FPGA | Yu-Ching Wu | d30_yuchingw_fpga |
| 31 | Linear Feedback Shift Register | Mihir Dhamankar | d31_mdhamank_lfsr |
| 32 | 4-bit CPU | Noah Gaertner | d32_ngaertne_cpu |
| 33 | Adder Architecture in Wokwi | Michael Gee | d33_mgee3_adder |
| 34 | Collatz Sequence Computer | Harrison Grodin | d34_hgrodin_collatz |
| 35 | Magnitude Comparator | Caroline Kasuba | d35_ckasuba_comparator |
| 36 | Floating Point Multiplier | Joseph Li | d36_jxli_fpmul |
| 37 | Calculator Chip | Sophia Li | d37_sophiali_calculator |
| 38 | PWM Signal Generator | Jason Lu | d38_jxlu_pwm |
| 39 | Hex to Seven-Segment | Kachi Onyeador | d39_oonyeado_sevenseg |
| 40 | Clock Domain Crossing FIFO | Jon Recta | d40_jrecta_asyncfifo |
| 41 | "Corral" Game | Michael Stroucken | d41_stroucki_corralgame |
| 42 | Hex to Seven-Segment | Samuel Sun | d42_qilins_sevenseg |
| 43 | Counter | Mason Xiao | d43_mmx_counter |
The tools used to merge and verify the designs with the multiplexer, as well as the resultant GDS files, can be found on GitHub: Tools/Designs Repo / Integration/GDS Repo
Author's Note: Most of these lectures were given in a highly-interactive fashion (with lots of whiteboarding and live demos) so some of these slides are fairly sparse (with the notable exception of lecture 8). However, we hope that the slides will be useful as an outline and a starting point for further study. Definitely be sure to check out the demos and resources as well!
Lecture Slides: lec01.pdf
Summary:
- Introduction to the course structure
- Why is chip design and computer architecture still growing and innovating?
- What are FPGAs and ASICs, and what are they used for?
- What are the different software tools needed to design chips?
Resources:
- NandGame (digital logic from first principles)
- NandLand Verilog Tutorials
- NandLand FPGA 101
- HDLBits (good review if your Verilog is rusty)
- Digital Design and Computer Architecture by Harris & Harris
Lecture Slides: lec02.pdf
Summary:
- Necessity of logic synthesis
- FPGA vs ASIC design flows
- Levels of abstraction in digital logic design
- Yosys synthesis and optimization passes (see "Synthesis Demos")
Demo: yosys-tutorial.md
Resources:
- Yosys manual
- Interactive design investigation
- SKY130 standard cell library
- Quine-McCluskey logic-optimization algorithm
Lecture Slides: lec03.pdf
Summary:
- Why open source chips are important?
- Security implications of a fully-auditable chip
- History of open source tapeouts
- What is TinyTapeout and how does it work?
- TinyTapeout project ideas
Resources:
- SkyWater PDK Release Talk (webinar)
- "45 Chips in 30 Days" (webinar)
- Sam Zeloof's Garage Fab
- TinyTapeout (bringing tapeouts to the masses)
- April 2023 TinyTapeout Submissions
Lecture Slides: lec04.pdf
Summary:
- FPGA Internals (CLBs/PLBs, Routing)
- How to design for FPGAs
- FPGA memory hierarchy and DSP blocks
- How to use hard IP in synthesis
- FPGA place-and-route algorithms
Resources:
- iCEBreaker FPGA Workshop
- NandLand FPGA 101
- NextPNR Paper
- ACM FPGA Conference Proceedings
- ULX3S FPGA Board
Lecture Slides: lec05.pdf
Summary:
- Verilog vs SystemVerilog vs VHDL
- Why simulation is important
- Software-hardware cosimulation using Verilator and CocoTB
- How to structure a testbench
Demo: simulation-demos
Resources:
- SV2V SystemVerilog Transpiler
- Verilator C++ Testbench Tutorial
- SystemVerilog / UVM in Verilator
- CocoTB Quickstart
- GTKWave Waveform Viewer
- PyVCD Python Waveform Parser
Lecture Slides: lec06.pdf
Summary:
- SKY130 process node
- How ASICs are designed from standard cells
- Design representation formats
- Steps in the RTL-to-GDS ASIC design flow (+ interactive exercise)
Resources:
- OpenLane Talk (webinar)
- OpenRAM Talk (webinar)
- "45 Chips in 30 Days" (webinar)
- Intro to Timing Analysis
- SiliWiz (online analog design tool)
- OpenLane Jupyter Demo
Lecture Slides: lec07.pdf
Summary:
- Taxonomy of hardware description languages
- Alternative HDL languages
- Demos of Amaranth and Chisel3 (+ interactive exercise)
- Automated system-on-chip generation tools
Resources:
- Chisel (Scala-based HDL) Interactive Tutorial
- Amaranth (Python-based HDL) Tutorial
- Amaranth (Python-based HDL) Advanced Tutorial
- HardCaml (OCaml-based HDL)
- PipelineC (auto-pipelined HDL)
- Google XLS (HLS toolchain)
- Merlin Compiler (HLS toolchain)
- MATLAB HDL Coder (Matlab-based hardware generator)
- LiteX SoC Generator
Lecture Slides: lec08.pdf
Summary:
- Unique challenges associated with hardware security
- Why are systems insecure?
- Side channel attacks and power-analysis
- Hidden hardware trojans in chips
- Shared tenancy attacks on cloud FPGAs
Resources:
- Reflections on Trusting Trust
- Joe Grand's Hardware Exploitation Series
- NewAE ChipWhisperer
- Hardware Hacking Handbook
- Undetectable Hardware Trojans Paper
- Trustworthy Self-Replicating RISC-V on FPGA
Lecture Slides: lec09.pdf
Summary:
- Mutation Cover for testbench coverage (+ interactive exercise)
- FPGA board recommendations for future projects
- More project ideas using FPGAs
- Getting involved with the online community
Resources
- Mutation Cover with Yosys
- ULX3S FPGA Board
- iCEBreaker FPGA Board
- Open Source Silicon Slack
- TinyTapeout Community
Lecture Slides: lec10.pdf
Summary:
- Chip packaging after manufacturing
- Package assembly and inspection
- JTAG + I/O boundary scan
- Scan chain insertion of internal registers
- Research literature and future directions of this space
Resources
- Open Circuits Book
- Intro to JTAG and Boundry Scan
- Fault, an Open Source DFT Toolchain
- WOSET Workshop Proceedings
If you found this content interesting, check out the linked resources above, get your hands on an FPGA development board, and submit your own project to the next Tiny Tapeout!
If you have any questions or suggestions, please reach out at: anish [-at-] anishsinghani [-dot-] com
Copyright 2023 Anish Singhani All Rights Reserved