atticusrussell/MIPS
A pipelined MIPS microprocessor written in VHDL and simulated in Xilinx Vivado targeting Basys3 board. Simplified MIPS instruction set. Made in RIT DSD2 (CMPE-260).
SystemVerilog
A pipelined MIPS microprocessor written in VHDL and simulated in Xilinx Vivado targeting Basys3 board. Simplified MIPS instruction set. Made in RIT DSD2 (CMPE-260).
SystemVerilog