/UVM_Verification

Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence

Primary LanguageSystemVerilog

UVM testbench with DPI integration, Assertions and Functional Coverage

In this project a complete verification testbench architecture for a result character conversion chip is constructed.

uvm_arch_v2

  • The testcase used for verification are the randomly generated input transactions for the DUT.
  • Further the functional verification is performed by comparing the output of the DUT with that of reference model.
  • To implement the reference model direct programming interface (DPI) functionality of SystemVerilog is used.
  • The reference model is the software implementation of the DUT written using the C-programming language.

Design Under test: RCC Unit used in DTMF Receiver

uvm_dut

100% Coverage Achieved for the DUT Verification

UVM_Coverage_Netlist200