hcpu-rv32i is a RISC-V RV32I compliant software CPU implementation using Haskell + Clash
hcpu-rv32 now support some basic instruction sets of RV32I.
However, some instruction sets, s.t. FENCE, FENCEI, ... are not implemented yet.
- R-type Format
- ADD
- SUB
- AND
- OR
- XOR
- SLL
- SRA
- SRL
- SLT
- SLTU
- I-type Format
- ADDI
- SLTI
- SLTIU
- XORI
- ORI
- ANDI
- SLLI
- SRAI
- SRLI
- JALR
- LB
- LH
- LW
- LBU
- LHU
- S-type Format
- SB
- SH
- SW
- B-type Format
- BEQ
- BNE
- BLT
- BGE
- BLTU
- BGEU
- U-type Format
- LUI
- AUIPC
- J-type Format
- JAL
- I-type Format
- FENCE
- FENCEI
- EBREAK
- ECALL
- CSRRC
- CSRRS
- CSRRW
- CSRRCI
- CSRRSI
- CSRRWI
- Add Test
- Refactor Codes
- Consider relation between
Vec n Instruction
and address space - Create fibonacci function and check it's execution
- Compile to Verilog-HDL
- Check working on compiled Verilog-HDL
- Check working on FPGA
Now, you have to hardcode instruction that you want to execute.
Please check some example in src/RV32I/Programs/Example.hs and test codes.
For example, If you want to run addImm
program in Example.hs, you can execute it by GHCi like bellow.
λ > Prelude.take 10 $ sample (cpu initCPUState (programmedRAM addImm) :: Signal System Registers)
...
or, you can use runCPU'
helper function.
λ > runCPU' addImm 0 10
sample
function generates infinite list of result of CPU execution, and addImm
code will loop by jumping same addresss, so you take some length from this.
You can see the 'fibonacci program' in src/RV32I/Programs/Fib.hs as a more complex example.
In this repository, we use Clash version 1.4.5
and can check its version as follows
stack run -- clash --version
Clash, version 1.4.5 (using clash-lib, version: 1.4.5)
Take too much time to compile this program. In my local computer, total compilation time is about 9h!
cabal run clash -- RV32I.Top --verilog
Up to date
Loaded package environment from /Users/mikiyaf/Documents/haskell/Clash/hcpu-rv32i/.ghc.environment.x86_64-darwin-8.10.7
GHC: Parsing and optimising modules took: 8.366s
GHC: Loading external modules from interface files took: 0.008s
GHC: Parsing annotations took: 0.010s
Clash: Parsing and compiling primitives took 0.176s
GHC+Clash: Loading modules cumulatively took 13.695s
Clash: Compiling RV32I.Top.topEntity
Clash: Normalization took 8h57m46.924s
Clash: Netlist generation took 2m0.349s
Clash: Total compilation took 9h0m3.538s
and generaed code is total 70000+ LoC verilog file.