bespoke-silicon-group/basejump_stl
BaseJump STL: A Standard Template Library for SystemVerilog
SystemVerilogNOASSERTION
Issues
- 3
commone interface stl
#694 opened by neilwang0913 - 0
SRAM TSMC 40 nm
#688 opened by amithmath - 2
- 1
Broken Links
#687 opened by Subashkatel - 31
- 0
Multiple latches
#497 opened by dpetrisko - 4
DT and RT getting stuck sometimes
#573 opened by yunusdawji - 2
Add code for FPGA side of bsg_link
#609 opened by taylor-bsg - 0
Move DMA memory modules to bsg_test
#444 opened by mrutt92 - 0
- 0
ADD "U R CRAZY" warnings when attempting to synthesize things that must absolutely be hardened
#448 opened by taylor-bsg - 0
long term change
#545 opened by taylor-bsg - 4
- 3
bsg_dmc_s timing parameters
#679 opened by infinitymdm - 4
Getting Started with BaseJump STL
#671 opened by ShvetankPrakash - 0
bsg_mem/bsg_mem_1rw_sync_mask_write_bit_from_1r1w.sv: Variable used before declaration
#674 opened by infinitymdm - 2
- 30
Double Trouble PCB Design
#430 opened by KarimHammad - 0
Release bsg_link FPGA implementation
#644 opened by dpetrisko - 5
Broken cache testbenches
#637 opened by BrendenPage - 2
bsg_cache.v ready_o may be yumi_o
#605 opened by BrendenPage - 2
Should be yumi_o not ready_o
#517 opened by taylor-bsg - 0
bsg_nonsynth_dramsim3 failing testbench
#622 opened by dpetrisko - 1
bsg_cache_to_test_dram does not support multiple outstanding reads per channel
#616 opened by dpetrisko - 9
- 2
Syntax errors in generated hard-macro-swapping verilog files when using Python3
#579 opened by derekcom17 - 2
- 4
bsg_cache optimization -- don't replay TL instruction if there is no TL instruction
#586 opened by dpetrisko - 1
bsg_comm_link_master_calib_skip_rom.v is broken
#598 opened by flaviens - 1
- 0
Problem with testing on `bsg_dataflow` modules
#574 opened by lomotos10 - 4
- 1
- 0
- 1
Hardcoded address width in bsg_cache_to_dram_ctrl
#532 opened by dpetrisko - 0
DMC TB params : remove hardcoded values.
#520 opened by akashnt4 - 2
Small fifo hardened power consumption
#512 opened by gaozihou - 8
Potential bug in hardened fifo module
#465 opened by Shashank-Vijay - 3
Circular Pointer X-pessimism Problem
#491 opened by gaozihou - 0
add parameter to clock gate the write data latch
#489 opened by taylor-bsg - 2
RealTrouble PCB Implementation
#482 opened by cmcjames - 0
Force bsg_cache_dma cache line alignment
#481 opened by dpetrisko - 1
defaults should be set to invalid
#470 opened by taylor-bsg - 2
just include verilator DPI clock gen, so testbenches don't have to double instantiate everything?
#462 opened by taylor-bsg - 9
BSG_ABSTRACT does not work for verilator toplevel
#446 opened by dpetrisko - 0
Consider (later) pulling ready low during reset.
#434 opened by taylor-bsg - 3
Incorrect comments on v_i/ready_o port in bsg_one_fifo
#428 opened by muwyse - 0
Should be bsg_yumi_link?
#427 opened by dpetrisko - 0
- 4
Other tools for BSG_VIVADO_SYNTH_FAILS
#420 opened by dpetrisko