Bespoke Silicon Group

Accelerating productive, PPA-optimal HW Design

Pinned Repositories

basejump_stl
BaseJump STL: A Standard Template Library for SystemVerilog
Language:SystemVerilog498 30 18396
bsg_bladerunner
Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
Language:Python36 15 1719
bsg_fakeram
fakeram generator for use by researchers who do not have access to commercial ram generators
Language:Python30 10 913
bsg_manycore
Tile based architecture designed for computing efficiency, scalability and generality
Language:SystemVerilog221 20 15858
bsg_motherboards
BaseJump Open-Source Hardware Accelerator Motherboards
Language:Verilog7 7 70
bsg_newlib_dramfs
newlib, but with a dram-based file system using LittleFS! Also known as Panic Room.
Language:C8 15 11
bsg_packaging
BaseJump Open-Source Hardware Accelerator Packages and Sockets
Language:Tcl8 13 82
bsg_pipeclean_suite
Language:Verilog10 5 01
bsg_replicant
BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade
Language:C++26 21 26020
bsg_sv2v
A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
Language:Python38 8 1210

Bespoke Silicon Group's Repositories

bespoke-silicon-group/basejump_stl
BaseJump STL: A Standard Template Library for SystemVerilog
Language:SystemVerilog498 30 18396
bespoke-silicon-group/bsg_manycore
Tile based architecture designed for computing efficiency, scalability and generality
Language:SystemVerilog221 20 15858
bespoke-silicon-group/bsg_sv2v
A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
Language:Python38 8 1210
bespoke-silicon-group/bsg_bladerunner
Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
Language:Python36 15 1719
bespoke-silicon-group/bsg_fakeram
fakeram generator for use by researchers who do not have access to commercial ram generators
Language:Python30 10 913
bespoke-silicon-group/bsg_replicant
BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade
Language:C++26 21 26020
bespoke-silicon-group/bsg_pipeclean_suite
Language:Verilog10 5 01
bespoke-silicon-group/bsg_newlib_dramfs
newlib, but with a dram-based file system using LittleFS! Also known as Panic Room.
Language:C8 15 11
bespoke-silicon-group/bsg_packaging
BaseJump Open-Source Hardware Accelerator Packages and Sockets
Language:Tcl8 13 82
bespoke-silicon-group/bsg_motherboards
BaseJump Open-Source Hardware Accelerator Motherboards
Language:Verilog7 7 70
bespoke-silicon-group/baseline
An Experimental Repository for BSG Bladerunner using CUDA Lite
Language:Makefile4 9 47
bespoke-silicon-group/bsg_ddr3_io
BaseJump DDR3 I/O Design
Language:Python4 16 1
bespoke-silicon-group/accelerator-debugger
A framework for building application-level debuggers for bleeding-edge hardware systems.
Language:Python3 7 15
bespoke-silicon-group/bsg_pearls
Open source IP blocks for SoCs and testing collateral. Often consists of compound instantiations of BaseJump STL or other blocks.
Language:SystemVerilog2 15 01
bespoke-silicon-group/gpgpu-sim_distribution
GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for features such as TensorCores and CUDA Dynamic Parallelism as well as a performance visualization tool, AerialVisoin, and an integrated energy model, GPUWattch.
Language:C++2 3 0
bespoke-silicon-group/hb_starlite
Language:Shell2 18 4
bespoke-silicon-group/ramulator
A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf
Language:C++2 2 0
bespoke-silicon-group/Galois
Galois: C++ library for multi-core and multi-node parallelization
Language:C++1 2 0
bespoke-silicon-group/riscv-gnu-toolchain
GNU toolchain for RISC-V, including GCC
Language:C1 2 01
bespoke-silicon-group/tvm
Open deep learning compiler stack for cpu, gpu and specialized accelerators
Language:Python1 3 11
bespoke-silicon-group/beebs
A set of benchmarks chosen to show the energy consumption of embedded devices under different conditions
Language:Makefile2 0
bespoke-silicon-group/bsg_idf_tools
Tools associated with IDF (IDEA Dimensionless Floorplan) format
Language:Python6 0
bespoke-silicon-group/GSOC-2019
Reshabh's GSOC project!
Language:C++5 0
bespoke-silicon-group/hb_hammerbench
HammerBlade Benchmarks
Language:C++
bespoke-silicon-group/hbpintool
Language:C++14 0
bespoke-silicon-group/llvm-project
The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. Note: the repository does not accept github pull requests at this moment. Please submit your patches at http://reviews.llvm.org.
Language:C++3 13
bespoke-silicon-group/pytorch
Tensors and Dynamic neural networks in Python with strong GPU acceleration
Language:C++2 0
bespoke-silicon-group/riscv-gcc
Language:C2 14
bespoke-silicon-group/RISCV32-GPU
GPU extension for RISCV 32
Language:C++2 0
bespoke-silicon-group/tiny-AES-c
Small portable AES128/192/256 in C
Language:C2 0