bespoke-silicon-group/bsg_sv2v
A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
PythonBSD-3-Clause
Issues
- 0
sv2v converter failed with AssertionError
#25 opened by sakundu - 1
Unimplemented SEQGEN
#23 opened by mjc0608 - 0
add formality checking =)
#20 opened by taylor-bsg - 1
- 1
always@ reduction fails in swerv design
#12 opened by tajayi - 1
- 3
Missing module top
#14 opened by tanglingshu - 2
minor bug: 'z is not converted back
#6 opened by taylor-bsg - 2
error out earlier
#4 opened by taylor-bsg - 1
Delete comments
#8 opened by stdavids - 2
[bug] small crash bug on test example
#3 opened by taylor-bsg