Verilog code simulating the asynchronous communication between a CPU and a Peripheral.
- brunovieira97 - Bruno Vieira
- gianunisinos - Gian Boschetti
Asynchronous communication between a CPU and a Peripheral is simulated in this Verilog project.
VerilogGPL-3.0
Verilog code simulating the asynchronous communication between a CPU and a Peripheral.