calyxir/calyx

Question about Section 3 of the paper

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xiuhu17 commented

As my knowledge, non-blocking assignment is always_ff in hdl(for example, SystemVerilog). The value from right hand side will not be shown in the left hand side immediately(the same cycle).
Screenshot 2024-06-05 at 6 27 08 PM

sampsyo commented

Hi there! I'm glad you're taking a look at the paper!

Could you please give a little more detail about what your question is here exactly? Not sure if this is what you're looking for, but assignments in Calyx are a little bit like always_comb in SystemVerilog, in the sense that they take place within a clock cycle, but they are not ordered, which is not true of always_comb but is kinda more like <=. So any analogy to Verilog is necessarily imperfect.

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xiuhu17 commented

Thanks for the reply!

I think you solved my confuse. It is stated as non-blocking since the assignment is not ordered.