Pinned Repositories
doctest
The fastest feature-rich C++11/14/17/20 single-header testing framework
fpga-network-stack
Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)
ntl
Networking Template Library for Vivado HLS
cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
10g-low-latency-ethernet
10G Low Latency Ethernet
awesome-hdl
Hardware Description Languages
awesome-hpp
A curated list of awesome header-only C++ libraries
awesome-python
A curated list of awesome Python frameworks, libraries, software and resources
AXOrderBook
A股订单簿工具，使用逐笔行情进行订单簿重建、千档快照发布、各档委托队列展示等，包括python模型和FPGA HLS实现。
basic_verilog
Must-have verilog systemverilog modules
captainliuy's Repositories
captainliuy/CLAP
C++ Library for FPGA Access and Programming
captainliuy/openFPGALoader
Universal utility for programming FPGA
captainliuy/open-nic-shell
captainliuy/Vitis_Libraries
Vitis Libraries
captainliuy/verilog-ethernet
Verilog Ethernet components for FPGA implementation
captainliuy/fpga-network-stack
Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)
captainliuy/websocketpp
C++ websocket client/server library
captainliuy/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
captainliuy/corsair
Control and Status Register map generator for HDL projects
captainliuy/open-rdma
RoCE v2 hardware implementation using Spinal HDL
captainliuy/awesome-python
A curated list of awesome Python frameworks, libraries, software and resources
captainliuy/SpinalHDL_CNN_Accelerator
CNN accelerator implemented with Spinal HDL
captainliuy/FSPX
captainliuy/veriloggen
Veriloggen: A Mixed-Paradigm Hardware Construction Framework
captainliuy/PeakRDL
Control and status register code generator toolchain
captainliuy/crcgen
Generator for CRC HDL code (VHDL, Verilog, MyHDL)
captainliuy/awesome-hpp
A curated list of awesome header-only C++ libraries
captainliuy/awesome-hdl
Hardware Description Languages
captainliuy/10g-low-latency-ethernet
10G Low Latency Ethernet
captainliuy/concurrentqueue
A fast multi-producer, multi-consumer lock-free concurrent queue for C++11
captainliuy/AXOrderBook
A股订单簿工具，使用逐笔行情进行订单簿重建、千档快照发布、各档委托队列展示等，包括python模型和FPGA HLS实现。
captainliuy/xkISP
xkISP：Xinkai ISP IP Core (HLS)
captainliuy/Chainsaw
a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communication and Crypto applications
captainliuy/hlslib
A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
captainliuy/basic_verilog
Must-have verilog systemverilog modules
captainliuy/wb2axip
Bus bridges and other odds and ends
captainliuy/pollnet
A collection of non-blocking(polling) network libs for Linux, also support solarflare APIs(Tcpdirect/Efvi)
captainliuy/FakeIt
C++ mocking made easy. A simple yet very expressive, headers only library for c++ mocking.
captainliuy/doctest
The fastest feature-rich C++11/14/17/20 single-header testing framework
captainliuy/ntl
Networking Template Library for Vivado HLS