Pinned Repositories
chisel-style-guide
A Style Guide for the Chisel Hardware Construction Language
coremarkpro-util-make-riscv
The utility files to port CoreMark-Pro to RISC-V.
fpga-zynq
Support for Rocket Chip on Zynq FPGAs
initramfs_linux_flow
This is a hacky tool for building a BBL+Linux+InitRAMFS image for RISC-V.
isa-analysis-tools
A set of scripts and tools that are helpful for analyzing different ISAs' code behavior.
riscv-boom-doc
Documentation for the BOOM processor
riscv-hpmcounters
A simple utility for doing RISC-V HPM perf monitoring.
riscv-pythia
A RISC-V superscalar front-end simulator.
Speckle
A wrapper for the SPEC CPU2006 benchmark suite.
TileCodeRayTracer
A simple ray tracer targeting both Tilera's TILE64 and x86 processors.
ccelio's Repositories
ccelio/chisel-style-guide
A Style Guide for the Chisel Hardware Construction Language
ccelio/Speckle
A wrapper for the SPEC CPU2006 benchmark suite.
ccelio/riscv-boom-doc
Documentation for the BOOM processor
ccelio/riscv-hpmcounters
A simple utility for doing RISC-V HPM perf monitoring.
ccelio/initramfs_linux_flow
This is a hacky tool for building a BBL+Linux+InitRAMFS image for RISC-V.
ccelio/riscv-pythia
A RISC-V superscalar front-end simulator.
ccelio/coremarkpro-util-make-riscv
The utility files to port CoreMark-Pro to RISC-V.
ccelio/TileCodeRayTracer
A simple ray tracer targeting both Tilera's TILE64 and x86 processors.
ccelio/fpga-zynq
Support for Rocket Chip on Zynq FPGAs
ccelio/isa-analysis-tools
A set of scripts and tools that are helpful for analyzing different ISAs' code behavior.
ccelio/qsub-fpga
Infrastructure for managing FPGA cluster via qsub.
ccelio/chisel
ccelio/generator-bootcamp
Generator Bootcamp Material: Learn Chisel the Right Way
ccelio/RemoteTech
Community developed continuation of Kerbal Space Program's RemoteTech mod.
ccelio/riscv-isa-manual
RISC-V Instruction Set Manual
ccelio/riscv-isa-sim
Spike, a RISC-V ISA Simulator
ccelio/riscv-pk
RISC-V Proxy Kernel
ccelio/riscv-tests
ccelio/riscv-torture
RISC-V Torture Test
ccelio/rocket
Rocket Microarchitectural Implementation of RISC-V ISA
ccelio/rocket-chip
Rocket Chip Generator
ccelio/testchipip