UC Berkeley Architecture Research

Berkeley, CA

Pinned Repositories

berkeley-hardfloat
Language:Scala269 53 2784
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Language:Scala1.5k 82 631598
chisel-tutorial
chisel tutorial exercises and answers
Language:Scala673 88 59194
chisel2-deprecated
Language:Scala388 92 32690
chiseltest
The batteries-included testing and formal verification library for Chisel-based RTL designs.
Language:Scala208 24 19070
dsptools
A Library of Chisel3 Tools for Digital Signal Processing
Language:Scala211 36 7538
fpga-zynq
Support for Rocket Chip on Zynq FPGAs
Language:Tcl387 71 102191
gemmini
Berkeley's Spatial Array Generator
Language:Scala694 29 176144
riscv-mini
Simple RISC-V 3-stage Pipeline in Chisel
Language:Scala506 39 28102
riscv-sodor
educational microarchitectures for risc-v isa
Language:Scala649 82 34152

UC Berkeley Architecture Research's Repositories

ucb-bar/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Language:Scala1.5k 82 631598
ucb-bar/gemmini
Berkeley's Spatial Array Generator
Language:Scala694 29 176144
ucb-bar/hammer
Hammer: Highly Agile Masks Made Effortlessly from RTL
Language:Python238 33 36652
ucb-bar/dsptools
A Library of Chisel3 Tools for Digital Signal Processing
Language:Scala211 36 7538
ucb-bar/chiseltest
The batteries-included testing and formal verification library for Chisel-based RTL designs.
Language:Scala208 24 19070
ucb-bar/testchipip
Language:Scala78 27 2959
ucb-bar/gemmini-rocc-tests
Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
Language:C49 13 1037
ucb-bar/RoSE
A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robotic system.
Language:Python32 16 04
ucb-bar/libgloss-htif
A libgloss replacement for RISC-V that supports HTIF
Language:C17 10 67
ucb-bar/shuttle
A Rocket-based RISC-V superscalar in-order core
Language:Scala16 13 02
ucb-bar/dosa
DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators
Language:Python12 13 01
ucb-bar/Baremetal-IDE
A submodule of Chipyard https://github.com/ucb-bar/chipyard
Language:HTML7 13 85
ucb-bar/spike-devices
Collection of device models for spike
Language:C++7 11 34
ucb-bar/rerocc
Language:Scala4 13 11
ucb-bar/Accelerated-TinyMPC
Model-predictive control for microcontrollers (fork mapping tinyMPC to gemmini or other HW accelerators)
Language:C++2 1 01
ucb-bar/Baremetal-llama
Language:C2 11 01
ucb-bar/Baremetal-NN
A tool for converting PyTorch models into raw C codes that can be executed standalone in a baremetal runtime on research chips.
Language:C2
ucb-bar/firrtl2
UC Berkeley Copy of the FIRRTL Compiler
Language:Scala2 12 03
ucb-bar/chipyard-cs152-sp24
Language:C1
ucb-bar/libgemmini
Gemmini extensions for Spike
Language:C++1 15 12
ucb-bar/mempress
Language:C1 15 01
ucb-bar/tsi
Standalone tethered serial interface (TSI) implementation with CLI utilities.
Language:Rust1 11 0
ucb-bar/Baremetal-IDE-bsp
Parent Repo: https://github.com/ucb-bar/Baremetal-IDE
Language:C11 62
ucb-bar/ethernet-wrapper
Wrapper for Ethernet Components
10 0
ucb-bar/iris-event-utils
Language:Python
ucb-bar/radiance
Rocket Chip Generator
Language:Scala0 01
ucb-bar/Retreat-Demo-Cartpole
Code for Cartpole demo for Sp24 SLICE Retreat
Language:Python
ucb-bar/riskybear-firmware
Language:Assembly
ucb-bar/riskybear-mechanical
10 0
ucb-bar/riskybear-PCB