Issues
- 0
iotesters.Driver has deprecated in Chisel 3.5.3, should this tutorial changed to ChiselStage?
#172 opened by gerayking - 2
- 0
"chisel-iotesters" -> "1.4.1+" in build.sbt breaks Vec code (which is also in your solutions)
#171 opened by FrancescoTerrosi - 0
Is there any method to prevent the generation of lot of directory when using chisel PeekPokeTester?
#170 opened by ken881015 - 0
- 3
not found: type SwitchContext
#166 opened by YongkangLi - 2
- 9
sbt run fails with EvalException
#164 opened by DDRDmakar - 0
Risc example broken with treadle backend
#159 opened by chick - 0
- 0
xorR is broken in chisel-tutorial
#152 opened by adoerflinger - 4
how to run chisel-tutorial in the IntelliJ IDE with Scala and SBT plug-ins?
#149 opened by Ravenwater - 2
why the code of VendingMachineSwitch.scala in the tutorial generate if-else statement instead of case statement
#151 opened by qgzln - 2
sbt run get error
#144 opened by botaichang - 0
- 1
Need a consistent naming convention on variables
#146 opened by iBug - 0
- 12
can I generate verilog without sbt ?
#143 opened by balanx - 11
question about Firrtl(IR) optimization
#142 opened by YingkunZhou - 6
sbt run problem
#124 opened by kaito0422 - 2
Error on generating Verilog
#141 opened by beatsnbytes - 2
error sbt run
#140 opened by ipere - 6
error with sbt run
#133 opened by eahmedsalman - 5
sbt run error
#128 opened by Arna-Maity - 0
- 1
how to compile chisel code to Verilog for fpga
#132 opened by jjtoms4s - 2
java.lang.Runtimeexception
#129 opened by jjtoms4s - 3
problem in build.sbt
#112 opened by poweihuang17 - 2
- 1
AdderTest.scala get a wrong testing
#117 opened by citrus-lemon - 1
Difference between 'to' and 'until' in for loop
#115 opened by pranith - 2
"File name too long" in sbt
#114 opened by 3100 - 7
Facing issue while generating verilog
#111 opened by Sairam-Ganti - 10
sbt problem
#81 opened - 0
synchronous memory description
#107 opened by schoeberl - 3
Probably typos in the Wiki?
#96 opened by schoeberl - 2
Absense of bc binary makes false error message
#106 opened by aurabindo - 2
Cann't generate verilog
#105 opened by zhangyl4991 - 4
when is a combinatorial construct
#95 opened by schoeberl - 3
Documentation on tutorial wrong: missing GCD.scala
#85 opened by dleach - 1
Error when running the examples
#88 opened by sorooshstrife - 7
Error in Using PeekPokeTester
#87 opened by MahdiNazemi - 3
Code in Wiki is dated
#80 opened by jackkoenig - 3
Generated VCD
#83 opened by davidwende - 0
solutions/Launcher.scala has a typo
#78 opened by MahdiNazemi - 1
- 1
README incorrect: No Mux2 in problems package
#67 opened by jcmartin - 2
discrepancy between Verilog and firrtl simulation
#66 opened by sols1 - 1
the first example does not work
#64 opened by sols1 - 1