Synhesis of V1_master

[rahul-rvm]

Hello ,

I am trying to Synthesis V1_master .

I have solved all errors only following error is coming in aib_top.v.

Error: /home/eitratest15/aib-phy-hardware-master/rev2/rtl/v1_master/c3aibadapt_wrap/rtl/aib_top.v:23: Illegal reference to memory i_test_c3adapt_scan_in. (VER-253)
Error: /home/eitratest15/aib-phy-hardware-master/rev2/rtl/v1_master/c3aibadapt_wrap/rtl/aib_top.v:23: Illegal reference to memory i_test_c3adapt_tcb_static_common. (VER-253)
Error: /home/eitratest15/aib-phy-hardware-master/rev2/rtl/v1_master/c3aibadapt_wrap/rtl/aib_top.v:23: Illegal reference to memory o_test_c3adapt_scan_out. (VER-253)
Error: /home/eitratest15/aib-phy-hardware-master/rev2/rtl/v1_master/c3aibadapt_wrap/rtl/aib_top.v:212: Illegal reference to memory o_test_c3adapt_scan_out. (VER-253)
Error: /home/eitratest15/aib-phy-hardware-master/rev2/rtl/v1_master/c3aibadapt_wrap/rtl/aib_top.v:212: Illegal reference to memory i_test_c3adapt_scan_in. (VER-253)

Can you provide support to resolve these errors.

Thanks and Regards,

Rahul

[xinyang2k]

Hi Rahul,

We are not supporting the synthesis at this point. But I looked at your error anyway, it looks like your tool has problem supporting two dimensional array as port. I would suggest you to get rid of this by setting the source files type to SystemVerilog.