chipsalliance/aib-phy-hardware

Issues

• unused port tclk_phy in v2.0/rev1

  #74 opened 5 months ago by nij-intel
  2

• DCC and DLL verilog code explanation

  #72 opened 5 months ago by CapucinedeBoissac
  5

• Clarify file hierarchy and versions vs. spec revisions

  #73 opened a year ago by CapucinedeBoissac
  5

• AVMM register description not complete?

  #75 opened a year ago by mhaedrich1
  1

• Please add M1S2_ROTATE to v2.0/rev1.1/dv/sims/run_compile_m1bca

  #70 opened 2 years ago by dkehlet
  0

• Please add a run_compile_bca2s2 script and testbench with M2S2_ROTATE to v2.0/rev1.1/dv/sims

  #71 opened 2 years ago by dkehlet
  0

• RX20 data is wrong when repair RX18,19 pins at v2.0/rev1/rtl/aib_channel.v

  #69 opened 2 years ago by tramphamsnps
  2

• Repair of TX0 pin does not work v2.0/rev1/rtl/aib_ioring.v

  #68 opened 2 years ago by tramphamsnps
  4

• sim_dcc and sim_dcc_static

  #66 opened 2 years ago by CapucinedeBoissac
  5

• emib_ch_m2s1.sv should have sl72 as NC, not tie_low

  #67 opened 2 years ago by dkehlet
  1

• AIB Adapter Word Marking and Word Assembly questions (part II)

  #64 opened 2 years ago by tramphamsnps
  3

• Test cases to run on an AIB 2.0 PHY

  #65 opened 2 years ago by dkehlet
  2

• Need emib_m1s2 and emib_m2s2 models for rotated West AIB 2.0

  #63 opened 3 years ago by dkehlet
  1

• Voltage level of *_RCV_CLK should be 0.9V or 0.4V

  #62 opened 3 years ago by nguyentheman90
  3

• Gen2 Mode control in AIB2.0

  #61 opened 3 years ago by clesnps
  6

• AIB Adapter Word Marking and Word Assembly question

  #59 opened 3 years ago by duytrinhkhac
  7

• Question about the rev1/ndsimslv/ testbench

  #34 opened 3 years ago by liuzixuan1212
  2

• AIB2.0 model connection mismatch

  #60 opened 3 years ago by clesnps
  1

• AIB2.0 model doesn’t support the receiver-domain transmit clock feature properly.

  #58 opened 3 years ago by lianaoliveira
  1

• Update DBI bit locations in the 2.0 model

  #57 opened 4 years ago by dkehlet
  2

• Ioring/Io_buffer Race Condition

  #31 opened 4 years ago by Gatorman11
  5

• v2.0 port should be called m_rx_align_done to match AIB 2.0 spec

  #56 opened 4 years ago by dkehlet
  1

• Writing read only reserved bits in csr

  #55 opened 4 years ago by b-sampson
  1

• wait_xfer_ready doesn't return for rev1/ndsimslv

  #48 opened 4 years ago by mkhazraee
  16

• open_source_aib_csr.xlsx, v2_slave tab needs example updates

  #49 opened 4 years ago by dkehlet
  2

• Add information about VCCIO(vccl) and VCCD(vcc, vcch) to Usage Guide

  #37 opened 4 years ago by dkehlet
  2

• Usage note needs update to AUX signals

  #32 opened 4 years ago by dkehlet
  1

• AIB Usage Note needs updates to examples for por and device detect

  #24 opened 4 years ago by dkehlet
  3

• Repair of TX0 pin has issue due to wrong connection

  #44 opened 4 years ago by khanhpvn
  2

• mismatch between code and spec in data calibration

  #43 opened 4 years ago by khanhpvn
  2

• Tristate behavior of aibcr3_analog.v

  #41 opened 4 years ago by rbaracka
  1

• AIB 1.2 spec is missing Alternate (Slave) Channel Bump Map

  #12 opened 4 years ago by dkehlet
  1

• Typos in AIB specification 1.2

  #13 opened 4 years ago by dkehlet
  1

• Remove master & slave references, replace with leader & follower

  #35 opened 4 years ago by dkehlet
  1

• v2 slave (follower) CSR differences

  #36 opened 4 years ago by dkehlet
  3

• Bump spreadsheet is missing Slave interface locations

  #11 opened 5 years ago by dkehlet
  1

• Synhesis of V1_master

  #33 opened 5 years ago by rahul-rvm
  1

• change DDR to SDR

  #17 opened 5 years ago by liuzixuan1212
  1

• Synthesis of AIB_Interface Master 2

  #29 opened 5 years ago by chandni-hash
  1

• Query for Synthesis

  #28 opened 5 years ago by rahul-rvm
  1

• v2 slave needs to daisy-chain i_osc_clk

  #19 opened 5 years ago by dkehlet
  1

• synthesis of the aib

  #4 opened 5 years ago by liuzixuan1212
  7

• Table 5 of AIB_Usage_Note_v1_2_2.pdf has errors in *adapter_rstn signal names

  #21 opened 5 years ago by dkehlet
  1

• Synthesis of AIB

  #9 opened 5 years ago by rahulrvm82
  1