chipsalliance/riscv-dv

Complex test generation for MMU,Branch

buraktoker opened this issue · 0 comments

Hello,

I am using a RISC-V core for thesis work and I want to test this designs branch unit, LSU and caches. My core dump sometimes during branch instructions in supervisor mode

I use these flags in yaml file to test it ,however no error comes.

gen_opts: >
+instr_cnt=150000
+num_of_sub_program=10
+directed_instr_0=riscv_load_store_rand_instr_stream,20
+directed_instr_1=riscv_loop_instr,10
+directed_instr_2=riscv_hazard_instr_stream,10
+directed_instr_3=riscv_load_store_hazard_instr_stream,5
+directed_instr_4=riscv_multi_page_load_store_instr_stream,20
+directed_instr_5=riscv_mem_region_stress_test,20
+directed_instr_6=riscv_jal_instr,5
+boot_mode=s

Is there any different flag or combination to stress these modules more?
Regards,