Error "UVM_FATAL" when trying to use eUVM port

[tuppi-ovh]

tested with eUVM: 1.0-beta25

I use these commands to compile/run:

cd euvm/build
make -j `nproc`
make run 

The compilation is ok. The running fails:

./riscv_instr_gen +UVM_VERBOSITY=NONE +random_seed=1 +UVM_TESTNAME=riscv.test.riscv_instr_base_test.riscv_instr_base_test +num_of_tests=1 +start_idx=0 +asm_file_name=out_2022-07-08/asm_test/riscv_rand_instr_test +instr_cnt=100000 +num_of_sub_program=5 \
+directed_instr_0=riscv.gen.riscv_load_store_instr_lib.riscv_load_store_rand_instr_stream,4 \
+directed_instr_1=riscv.gen.riscv_load_store_instr_lib.riscv_hazard_instr_stream,4 \
+directed_instr_2=riscv.gen.riscv_load_store_instr_lib.riscv_load_store_hazard_instr_stream,4 \
+directed_instr_3=riscv.gen.riscv_load_store_instr_lib.riscv_multi_page_load_store_instr_stream,4 \
+directed_instr_4=riscv.gen.riscv_load_store_instr_lib.riscv_mem_region_stress_test,4 \
+directed_instr_5=riscv.gen.riscv_directed_instr_lib.riscv_jal_instr,4 \
+directed_instr_6=riscv.gen.riscv_loop_instr.riscv_loop_instr,4
Using random_seed: 1
[ESDL!test] Starting Phase: BUILD
[ESDL!test] Starting Phase: CONFIGURE
[ESDL!test]*No default timePrecision specified; setting timePrecision to 1.psec
[ESDL!test]*No default timeUnit specified; setting timeUnit to 1.nsec
[ESDL!test] Starting Phase: BIND
[ESDL!test] Start of Simulation
UVM_INFO ../euvm/src/uvm/base/uvm_root.d(1251) @ 0: reporter [UVM/RELNOTES] 
  ***********       IMPORTANT RELEASE NOTES         ************

  This implementation of the UVM Library deviates from the 1800.2-2020
  standard.  See the DEVIATIONS.md file contained in the release
  for more details.

----------------------------------------------------------------
Accellera:1800.2-2020:UVM:1.0

All copyright owners for this kit are listed in NOTICE.txt
All Rights Reserved Worldwide
----------------------------------------------------------------

      (Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_WARNING @ 0: reporter [BDTYP] Cannot create a component of type 'riscv.test.riscv_instr_base_test.riscv_instr_base_test' because it is not registered with the factory.
UVM_FATAL ../euvm/src/uvm/base/uvm_root.d(373) @ 0: reporter [INVTST] Requested test from command line +UVM_TESTNAME=riscv.test.riscv_instr_base_test.riscv_instr_base_test not found.
UVM_INFO ../euvm/src/uvm/base/uvm_report_server.d(971) @ 0: reporter [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

** Report counts by severity
UVM_TRACE :    0
UVM_FATAL :    1
UVM_ERROR :    0
UVM_WARNING :    1
UVM_INFO :    1
** Report counts by id
[BDTYP]     1
[INVTST]     1
[UVM/RELNOTES]     1

[ESDL!test] Shutting down all the Routine threads
[ESDL!test] Shutting down all the active Tasks
[ESDL!test] Simulation Complete
[ESDL!test] Total Run Time: 0.000776.sec
^Cmakefile:150: recipe for target 'run' failed
make: *** [run] Interrupt