cookies2314

cookies2314's Stars

• WalkerLau/Accelerating-CNN-with-FPGA

  This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.

  Language:C++725185

• CMA-ES/pycma

  Python implementation of CMA-ES

  Language:Jupyter Notebook1.1k178

• pku-liang/AMOS

  Automatic Mapping Generation, Verification, and Exploration for ISA-based Spatial Accelerators

  Language:Python10210

• scalesim-project/scale-sim-v2

  Repository to host and maintain scale-sim-v2 code

  Language:Python22998

• ShahariarRabby/Scheduling_algo

  Operating System Scheduling algorithms, FCFS and SJF

  Language:Python511

• SamsungLabs/Sparse-Multi-DNN-Scheduling

  Open-source artifacts and codes of our MICRO'23 paper titled “Sparse-DySta: Sparsity-Aware Dynamic and Static Scheduling for Sparse Multi-DNN Workloads”.

  Language:Python32

• agongee/prema_sim

  prema simulation

  Language:Python9

• MPSLab-ASU/ML-Accelerators

  Topics in Machine Learning Accelerator Design

  5312

• simgrid/simgrid

  MIRROR of the SimGrid framework, for the simulation of distributed applications (Clouds, HPC, Grids, IoT and others). Most of the dev occurs on FramaGit.

  Language:C++16791

• FishermanLee/Energy-efficient-Hybrid-flow-shop

  This is source code of paper Multi-objective energy-efficient hybrid flow shop scheduling using Q-learning and GVNS driven NSGA-II.

  Language:Python15

• mrocklin/heft

  A static scheduling heuristic

  Language:Python4729

• 0x333333/HEFT

  Heterogeneous Earliest Finish Time (or HEFT) is a heuristic to schedule a set of dependent tasks onto a network of heterogeneous workers taking communication time into account.

  Language:C126

• mackncheesiest/heft

  Implementation of HEFT (Heterogeneous Earliest Finish Time) DAG Scheduling Algorithm in Python

  Language:Jupyter Notebook249

• pku-liang/HASCO

  agile hardware-software co-design

  Language:Python448

• GuoningHuang/FPGA-CNN-accelerator-based-on-systolic-array

  2023集创赛国二，紫光同创杯。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。

  Language:Verilog1169

• neasotho/SystolicArray_FPGA

  Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board

  Language:Tcl93

• hyupupup/conv_systolic_array

  (Verilog) A simple convolution layer implementation with systolic array structure

  Language:Verilog12

• luckiness/SparseMatrix

  稀疏矩阵的压缩存储及其转置

  Language:C++1

• delsin97/matrix

  稀疏矩阵存储格式

  Language:C1

• XiaosongAI/Parallel-SpMV

  稀疏矩阵-向量乘的并行优化算法（OpenMP，AVX）

  Language:C101