Issues
- 1
ASIC flow tutorial link is broken
#186 opened by ted-xie - 4
a small confusion of other language model support
#185 opened by hsqforfun - 3
possible bug in pclib/ifcs/ValRdyBundle.py
#183 opened by 3gx - 2
pymtl doesn't correctly register combinational blocks that write to slices of an OutPort
#182 opened by Xaec6 - 0
- 0
sext(concat()) does not translate
#178 opened by wizard97 - 0
Python list slicing translation
#177 opened by wizard97 - 1
Failed Installation
#176 opened by MattCatz - 15
- 6
Use apt-get install flex-old instead of flex
#168 opened by wizard97 - 8
when use, there is an error list index out of range in metaclasses.py in the floder named model
#173 opened by tristantian - 0
Help with design low-level HDL language
#171 opened by XVilka - 3
will pymtl be ported to Python3
#167 opened by CFAndy - 0
pymtl does check ".value" for single level Wire/OutPort but doesn't for the second level within message type
#162 opened by jsn1993 - 1
Verilog translation
#147 opened by Abhinav117 - 0
The order of test matters if this is correct.
#156 opened by jsn1993 - 0
The order of test matters. I think this is a bug
#157 opened by jsn1993 - 3
- 5
- 4
- 2
connecting wire slice to wire slice seems not to work
#144 opened by cbatten - 0
A minor bug (or functional extensions) of range select
#143 opened by jsn1993 - 2
The link to the research paper in README is wrong
#142 opened by derekchiang - 0
Verilog Translation Bug: Accessing fields from array of PortBundles not working
#141 opened by stevedai - 0
PyMTL keywords
#140 opened by ss2783 - 0
- 0
Imported VerilogModel wrappers won't dump *.verilator.vcd when vcd_file is set
#135 opened by dmlockhart - 0
- 0
Throw useful Error during translation when non-literal Bits constructors encountered.
#123 opened by dmlockhart - 0
Type inference from signal lists translate into temporaries with incorrect bitwidth
#136 opened by dmlockhart - 1
Gcd RTL example generates inferred latches
#138 opened by gl387 - 0
- 0
Models using BitStructs don't return BitStruct objects when translated to Verilog
#132 opened by dmlockhart - 0
Support `s.connect()` with constant `Bits` object
#126 opened by cbatten - 0
Verilog translated models fail if using a BitStruct defined in a non-global scope
#133 opened by dmlockhart - 0
- 0
SimulatorTool detects sensitivity list incorrectly for Bits in @combinational blocks
#128 opened by dmlockhart - 0
Add checking to detect multiple identical assignments/multiple assignments to the same signal.
#127 opened by dmlockhart - 0
PortBundles cannot contain lists
#125 opened by dmlockhart - 0
- 1
- 0
- 0
Add check during simulator construction for assigning to .value in @tick or .next in @combinational
#121 opened by dmlockhart - 0
Verilator model cache does not recompile if VCD dumping is enabled/disabled
#119 opened by dmlockhart - 0
- 2
- 0
Using reg as module name causes verilator error
#117 opened by cbatten - 0
Add support for arithmetic right shift
#116 opened by dmlockhart - 0
- 0
Remove `v=` and `w=` from `__repr__`
#114 opened by cbatten