Pinned Repositories
cu-gr
CUGR, VLSI Global Routing Tool Developed by CUHK
cu-gr-2
CULS
GPU-based logic synthesis tool
dr-cu
Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
GCS-Timer
neural-ilt
Neural-ILT, An End-to-end Learning-based Mask Optimizer
REST
REST, a reinforcement learning framework for constructing rectilinear Steiner Minimum tree (RSMT)
ripple
Pin-Accessible Legalization for Mixed-Cell-Height Circuits
ripple-fpga
RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA
Xplace
Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization
CUHK EDA's Repositories
cuhk-eda/dr-cu
Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
cuhk-eda/cu-gr
CUGR, VLSI Global Routing Tool Developed by CUHK
cuhk-eda/Xplace
Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization
cuhk-eda/ripple-fpga
RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA
cuhk-eda/CULS
GPU-based logic synthesis tool
cuhk-eda/neural-ilt
Neural-ILT, An End-to-end Learning-based Mask Optimizer
cuhk-eda/REST
REST, a reinforcement learning framework for constructing rectilinear Steiner Minimum tree (RSMT)
cuhk-eda/cu-gr-2
cuhk-eda/ripple
Pin-Accessible Legalization for Mixed-Cell-Height Circuits
cuhk-eda/GCS-Timer
cuhk-eda/A2-ILT
cuhk-eda/split-extract
Heterogeneous Feature Extraction for Split Manufactured Layouts with Routing Perturbation
cuhk-eda/split-attack
Deep Learning Analysis for Split Manufactured Layouts with Routing Perturbation