davidgussler/PeakRDL-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

PeakRDL-regblock

Compile SystemRDL into a SystemVerilog control/status register (CSR) block.

For the command line tool, see the PeakRDL project.

Documentation

See the PeakRDL-regblock Documentation for more details