dg2300

Pre Si Verification Engineer

Pinned Repositories

AXI_WB_TB
Basic UVM Testbench to verify AXI stream spec design. Added a wishbone BFM to mimic Wishbone design.
Language:Verilog2 1 00
Machine-Learning-Practice
This repository contains all my practice projects with Daniel and Andrei from Udemy for future reference, Complete Machine Learning & Data Science Bootcamp 2023
Language:Jupyter Notebook00
PULSEDETEC_OVMTB
Simple Pulse detector RTL and OVM_TB
Language:SystemVerilog00
UVM-TB-PRACTICE
Code Dump of Complete End to End Test Benches I practiced from references on Udemy and others.
Language:SystemVerilog00

dg2300/AXI_WB_TB
Basic UVM Testbench to verify AXI stream spec design. Added a wishbone BFM to mimic Wishbone design.
Language:Verilog2 1 00
dg2300/Machine-Learning-Practice
This repository contains all my practice projects with Daniel and Andrei from Udemy for future reference, Complete Machine Learning & Data Science Bootcamp 2023
Language:Jupyter Notebook00
dg2300/PULSEDETEC_OVMTB
Simple Pulse detector RTL and OVM_TB
Language:SystemVerilog00
dg2300/UVM-TB-PRACTICE
Code Dump of Complete End to End Test Benches I practiced from references on Udemy and others.
Language:SystemVerilog00