This paper presents a design of mixed signal on step-up converter to boost the input voltage. The step-up converter presented here offers a good efficiency performance. The proposed converter is designed in eSim tool, makerchip and Verilator.
fig1: schematic diagram of boost converter
fig2: circuit diagram of boost converter
fig3: waveform
A step-up converter is also known as boost converter, as the name suggests it steps up the input voltage to higher voltage, since the power is always conserved therefore the current in the output is lower than the input current and thus power is conserved. A typical step-up converter consists of a switch (transistor) and a diode as a semiconductor device, and storing element: inductor and a capacitor, the former is to store electrical energy in the form of magnetic energy and the later is to smooth the output voltage i.e., to filter out the ripple. The working principle of the step-up converter can be explained as follows
- When the transistor is ON state, current starts flowing through the inductor stores electric energy by generating magnetic field around it.
- When the transistor is turned OFF, inductor will pump out its stored energy through the diode and current will start flowing through it[2]. At higher switching speed inductor will not be able to discharge fully in between charging stages which as a result, a voltage higher than the input voltage will be developed at its output. Using Verilog the PWM signal can be generated to drive the gate of the transistor, thus a mixed signal design.
It is an open source Electronics Design Automation by FOSSEE, IIT Bombay. It is made using NgSpice and Kicad.
More at:
https://esim.fossee.in/home
It is used for spice simulations, it is an Open Source Software.
For more details visit:
http://ngspice.sourceforge.net/docs.html
It is an Online Web Browser IDE for Verilog/System-Verilog/TL-Verilog Simulation.
More details here
https://www.makerchip.com/
It is a tool used to convert Verilog code to C++ objects. Visit: https://www.veripool.org/verilator/
NOTE: For switching purpose a BJT is used, however a power n-channel MOSFET can also be used for that a model file must be created in eSim beforehand
fig4: schematic diagram of stepup converter
fig5: netlists
fig6: waveform of stepup converter
fig7: circuit diagram of stepup converter
fig8: verilog code
\TLV_version 1d: tl-x.org
\SV
/* verilator lint_off UNUSED*/ /* verilator lint_off DECLFILENAME*/ /* verilator lint_off BLKSEQ*/ /* verilator lint_off WIDTH*/ /* verilator lint_off SELRANGE*/ /* verilator lint_off PINCONNECTEMPTY*/ /* verilator lint_off DEFPARAM*/ /* verilator lint_off IMPLICIT*/ /* verilator lint_off COMBDLY*/ /* verilator lint_off SYNCASYNCNET*/ /* verilator lint_off UNOPTFLAT */ /* verilator lint_off UNSIGNED*/ /* verilator lint_off CASEINCOMPLETE*/ /* verilator lint_off UNDRIVEN*/ /* verilator lint_off VARHIDDEN*/ /* verilator lint_off CASEX*/ /* verilator lint_off CASEOVERLAP*/ /* verilator lint_off PINMISSING*/ /* verilator lint_off BLKANDNBLK*/ /* verilator lint_off MULTIDRIVEN*/ /* verilator lint_off WIDTHCONCAT*/ /* verilator lint_off ASSIGNDLY*/ /* verilator lint_off MODDUP*/ /* verilator lint_off STMTDLY*/ /* verilator lint_off LITENDIAN*/ /* verilator lint_off INITIALDLY*/
//Your Verilog/System Verilog Code Starts Here:
`timescale 1ns / 1ps
module yt_pwm(
input clk,
output led
);
// Create a simple counter
reg [7:0] counter =0;
always @ (posedge clk) begin
if (counter < 5000) counter<= counter +1; // count until 5000
else counter <=0;// reset counter
end
// create 80% duty cycle
assign led = (counter<80) ? 1:0; // assign LED to 1 if counter value is less than 80
endmodule
//Top Module Code Starts here:
module top(input logic clk, input logic reset, input logic [31:0] cyc_cnt, output logic passed, output logic failed);
logic led;//output
//The $random() can be replaced if user wants to assign values
yt_pwm yt_pwm(.clk(clk), .led(led));
\TLV
//Add \TLV here if desired
\SV
endmodule
fig9: makerchip plot
fig10: netlists
fig11: input voltage
fig12: output voltage
fig13: GAW plots
- Open eSim
- Run NgVeri-Makerchip
- Add top level verilog file in Makerchip Tab
- Click on NgVeri tab
- Add dependency files
- Click on Run Verilog to NgSpice Converter
- Debug if any errors
- Model created successfully
- Open a new terminal
- Clone this project using the following command:
git clone https:///github.com/dilipboidya/boost-converter.git - Change directory:
cd eSim_project_files/sc_test - Run NgSpice:
ngspice sc_test.cir.out - To run this project in eSim:
- Run eSim
- Load the project
- Open eeSchema
- FOSSEE, IIT Bombay
- Steve Hoover, Founder, Redwood EDA
- Kunal Ghosh, Co-founder, VSD Corp. Pvt. Ltd. - kunalpghosh@gmail.com
- Sumanto Kar, eSim Team, FOSSEE
- Jaber Abu-Qahouq and Issa Batarseh, "Generalized Analysis of Soft-Switching DC-DC Converters", ISCAS 2000 - IEEE International Symposium on Circuits and Systems, May 2831, 2000, Geneva, Switzerland, pp. 507-510.
- M. Ghanbari and S. M. Hosseini, "DC/DC boost converter design and development based on asynchronously paralleled switches," 2008 IEEE International Conference on Industrial Technology, 2008, pp. 1-5, doi: 10.1109/ICIT.2008.4608713.
- Eric Coates, "Boost Converter,Boost converter Operation" https://learnabout-electronics.org/PSU/psu32.php [accessed Feb. 28 2022]