Pinned Repositories
1000base-x
1000BASE-X IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS)
32-bit-Multiplier-design-using-transistor-level-Digital-Gates
This project was performed on the completion of our B. Tech 4th Semester Summer Training cum Academic Internship Programme on "RISC-V based 32-bit Digital Processor Design using SPICE" under E&ICT Academy IIT Guwahati and Assam Science & Technology University, Guwahati under TEQIP III in association with VLSI Expert
activecore
Hardware generation library based on "Kernel IP" (KIP) cores: programmable execution kernels inferred from microarchitectural templates
ADL
Architecture Description Language compiler for Orange C
alive2
Automatic verification of LLVM optimizations
amaranth
A modern hardware definition language and toolchain based on Python
arxiv-reference-graph
AUTOMATED-CIRCUIT-DESIGNER
“AUTOMATED CIRCUIT DESIGNER” can be used to design logic circuits. It reduces the Boolean expression & generate circuit diagram. It makes circuit construction easy & fast.
autowiring
Export an auto wiring build on circuit CAD to svg (Scalable Vector Graphics)
avr-ic-tester-v2
Chip tester
dingzex's Repositories
dingzex/activecore
Hardware generation library based on "Kernel IP" (KIP) cores: programmable execution kernels inferred from microarchitectural templates
dingzex/ADL
Architecture Description Language compiler for Orange C
dingzex/alive2
Automatic verification of LLVM optimizations
dingzex/chisel3
Chisel 3: A Modern Hardware Design Language
dingzex/compiler-explorer
Run compilers interactively from your web browser and interact with the assembly
dingzex/coredsl2tablegen
CoreDSL to Tablegen converter / code generator
dingzex/d3-hwschematic
D3.js and ELK based schematic visualizer
dingzex/Digital-IDE
All in one vscode plugin for HDL development
dingzex/eide
An embedded development environment for mcs51/stm8/avr/cortex-m/riscv on VsCode.
dingzex/elixir
Elixir is a dynamic, functional language for building scalable and maintainable applications
dingzex/firrtl-
Provides dot visualizations of chisel/firrtl circuits
dingzex/gdbgui
Browser-based frontend to gdb (gnu debugger). Add breakpoints, view the stack, visualize data structures, and more in C, C++, Go, Rust, and Fortran. Run gdbgui from the terminal and a new tab will open in your browser.
dingzex/gef
GEF (GDB Enhanced Features) - a modern experience for GDB with advanced debugging capabilities for exploit devs & reverse engineers on Linux
dingzex/hdlConvertorAst
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
dingzex/HDLGen
HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve
dingzex/hwtSimApi
RTL simulator bindings for Python and RTL simulator in python
dingzex/LLVM-9.0-Learner-Tutorial
A blog for LLVM(v9.0.0 or v11.0.0) beginner, step by step, with detailed documents and comments. Record the way I learn LLVM and accomplish a complete project for FPGA High-Level Synthesis with it.
dingzex/llvm-project
The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. Note: the repository does not accept github pull requests at this moment. Please submit your patches at http://reviews.llvm.org.
dingzex/manual
Reference manual for ForwardCom instruction set and software standards
dingzex/mipt-mips
Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs
dingzex/OpenTCAM
An open-source Ternary Content Addressable Memory (TCAM) compiler.
dingzex/ravenoc
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
dingzex/rggen
Code generation tool for configuration and status registers
dingzex/RISC-V-ISA-
A graphical processor simulator and assembly editor for the RISC-V ISA
dingzex/RTLflow
A GPU acceleration flow for RTL simulation with batch stimulus
dingzex/rvcc
Standalone C compiler for RISC-V and ARM
dingzex/stlib
dingzex/t1
dingzex/tydi-lang
dingzex/warp-v
WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.